Evolution Of Equalization Techniques In High-Speed SerDes For Extended Reaches

As data rates escalate, so does the need for more advanced signal processing capabilities.


The relentless demand for massive amounts of data is accelerating the pace of high-performance computing (HPC) within the high-speed Ethernet realm. This escalation, in turn, intensified the complexity associated with designing networking SoCs, including switches, NICs, retimers, and pluggable modules. Such growth is accelerating the demand for bandwidth hungry applications to transition from 400G to 800G and eventually to 1.6T Ethernet. In terms of SerDes data rates, this evolution translates to a surge from 56G to 112G to 224G per lane.

Before 56G SerDes, the dominant form of signaling was Non-Return-to-Zero (NRZ), which uses encoded binary data as a series of high and low voltage levels, with no returning to zero voltage level in between. NRZ signaling typically uses analog circuitry due to its low latency, making it ideal for high-speed applications.

However, as the data rates continued escalating, so did the need for more advanced signal processing capabilities. Digital circuits began to take precedence in SerDes designs from 56G to 112G to 224G. Digital signal processing (DSP) circuits enabled advanced signal processing, such as equalization, clock and data recovery (CDR), and adaptive equalization, became crucial in ensuring reliable high-speed data transmission. In addition, the push for lower power consumption and smaller form factor led to the wider adoption of digital SerDes circuits, which consume less power and can be implemented using smaller transistors, lending themselves to high-density integration.

Pulse Amplitude Modulation with four levels (PAM4) has since emerged as the preferred signaling method for high-speed communication systems, given its ability to transmit more data per symbol and its superior energy efficiency. That said, PAM4 signaling necessitates more intricate signal processing techniques to mitigate the effects of signal degradation and noise, ensuring the reliable recovery of transmitted signals at the receiver’s end. This article delves into the various DSP techniques employed in PAM4 SerDes.

Fig. 1: PAM4 DSP for 112G and beyond.

Equalization, clock recovery, and advanced DSP techniques in PAM4 SerDes


Equalization plays a vital role in the PAM4 SerDes DSP circuit. The equalization circuitry compensates for the signal degradation caused by channel impairments such as attenuation, dispersion, and crosstalk. Various methods can allow for the implementation of PAM4 equalization, such as:

  • Feedforward Equalization (FFE)
  • Decision-Feedback Equalization (DFE)
  • Adaptive Equalization

Feedforward Equalization (FFE) is a type of equalization that compensates for the signal degradation by amplifying or attenuating specific frequency components of the signal. FFE is implemented using a linear filter, which boosts or attenuates the high-frequency components of the signal. The FFE circuit uses an equalizer tap to adjust the filter coefficients. The number of taps determines the filter’s complexity and its ability to compensate for the channel impairments. FFE can compensate for channel impairments such as attenuation, dispersion, and crosstalk. However, FFE is not effective in mitigating inter-symbol interference (ISI).

Decision-Feedback Equalization (DFE) is a more advanced form of equalization that compensates for the signal degradation caused by ISI, a phenomenon in which the signal’s energy from previous symbols interferes with the current symbol, which causes distortion. DFE works by subtracting the estimated signal from the received signal to cancel out the ISI. The DFE circuit uses both feedforward and feedback taps to estimate and cancel out the ISI. The feedback taps compensate for the distortion caused by the previous symbol, and the feedforward taps compensate for the distortion caused by the current symbol. Although DFE is effective at mitigating ISI, it requires more complex circuitry than FFE.

Adaptive Equalization is a technique that automatically adjusts the equalization coefficients based on the channel’s characteristics. Employing an adaptive algorithm, it estimates the channel characteristics and updates the equalization coefficients to optimize the signal quality. The Adaptive Equalization circuit uses a training sequence to estimate the channel response and adjust the equalizer coefficients. Circuit can adapt to changing channel conditions, making it effective in mitigating various channel impairments.

Clock and Data Recovery (CDR)

Clock and Data Recovery (CDR) is another essential function of the PAM4 SerDes DSP circuit. The task of CDR circuitry consists of extracting the clock signal from the incoming data stream to synchronize the data at the receiver end. In PAM4, the clock extraction process posed a challenge due the increased number of signal transitions, making it difficult to distinguish the clock from the data. Different techniques such as Phase-Locked Loop (PLL) and Delay-Locked Loop (DLL) can be used for PAM4 CDR.

PLL is a technique that locks the oscillator frequency to the incoming signal’s frequency. The PLL measures the phase difference between the incoming signal and the oscillator and adjusts the oscillator frequency to match the incoming signal’s frequency. The PLL circuit uses a Voltage-Controlled Oscillator (VCO) and a Phase Frequency Detector (PFD) to generate the clock signal. In PAM4 SerDes, PLL-based CDR is the more common choice due to its noise robustness and better jitter performance compared to its DLL-based counterpart.

On the other hand, DLL is a technique that measures the time difference between the incoming signal and the reference signal and adjusts the phase of the incoming signal to align with the reference signal. The DLL circuit uses a delay line and a Phase Detector (PD) to generate the clock signal. DLL-based CDR is less frequently used in PAM4 SerDes due to its susceptibility to noise and has worst jitter performance compared to PLL-based CDR.

Advanced DSP techniques

Maximum Likelihood Sequence Detection (MLSD) is a technique employed to improve signal quality and mitigate channel impairments in high-speed communication systems requiring very long reaches. MLSD, a digital signal processing technique, leverages statistical models and probability theory to estimate the transmitted data sequence from the received signal.

MLSD works by generating all possible data sequences and comparing them with the received signal to find the most likely transmitted sequence. The MLSD algorithm uses the statistical properties of the signal and channel to calculate the likelihood of each possible data sequence, and the sequence with the highest likelihood is selected as the estimated transmitted data sequence.

While MLSD is a complex and computationally intensive technique that requires significant processing power and memory, it can provide significant improvements in signal quality and transmission performance. This is particularly true in channels with high noise, interference, and dispersion.

Fig. 2: Need for MLSD: Channel Library of 40+ dB IL equalized by 224G SerDes.

There are several variants of MLSD, including:

  • Viterbi Algorithm
  • Decision Feedback Sequence Estimation (DFSE)
  • Soft-Output MLSD

The Viterbi Algorithm, a popular MLSD algorithm, uses a trellis diagram to generate all possible data sequences and find the most likely sequence. The Viterbi Algorithm can provide excellent performance in channels with moderate noise and ISI, but it may suffer from error propagation in severe channel conditions.

DFSE, another MLSD algorithm, uses feedback from the decision output to improve the sequence estimation accuracy. DFSE can provide better performance than the Viterbi Algorithm in channels with high ISI and crosstalk, but it requires more complex circuitry and higher processing power.

Soft-Output MLSD, a variant of MLSD, provides probabilistic estimates of the transmitted data sequence. When combined with FEC techniques such as LDPC, it can provide significant improvements in the error-correction performance of the system. Although Soft-Output MLSD requires additional circuitry to generate the soft decisions, it can provide significant benefits in terms of signal quality and error-correction capabilities.

Forward Error Correction techniques

Forward Error Correction (FEC) techniques, in addition to DSP methods, add redundant data to the transmitted signal to detect and correct errors at the receiver end. FEC is an effective technique to improve the signal quality and ensure reliable transmission. Several FEC techniques can be used, including Reed-Solomon (RS) and Low-Density Parity-Check (LDPC).

RS is a block code FEC technique that adds redundant data to the transmitted signal to detect and correct errors. Because of its simplicity, efficiency, and robust error-correction capabilities, RS is a widely used FEC technique in PAM4 SerDes. LDPC, on the other hands, is a more advanced FEC technique that uses a sparse parity-check matrix.

Defining the future of 224G SerDes: A focus on PAM4 and MLSD DSP

In summary, both the IEEE 802.3df working group and the Optical Internetworking Forum (OIF) consortium are focused on the definition of the 224G interface.  To achieve 224G, the analog front-end bandwidth has increased by 2X for PAM4 or by 1.5X for PAM6. The demand for an ADC with improved accuracy and reduced noise is required. Stronger equalization is needed to compensate for the additional loss due to higher Nyquist frequency, with more taps in the FFE and DFE. MLSD advanced DSP will provide significant improvements in signal quality and transmission performance at 224G. MLSD algorithms, including Viterbi Algorithm, DFSE, and Soft-Output MLSD can be used to improve the sequence estimation accuracy and mitigate channel impairments such as noise, interference, and dispersion. However, as MLSD algorithms demand significant processing power and memory, careful consideration in choosing advanced DSP will help to strike a balance between performance, power, latency in C2M and cabled host applications.

Over many generations of High-Speed SerDes, Synopsys has been at the forefront of SerDes IP development, playing an integral role in defining PAM4 solution with DSP at 224G. Synopsys has a silicon-proven 224G Ethernet solution that customers can reference to achieve their own silicon success. Synopsys provides a complete solution with 224G Ethernet PHY, PCS, and MAC with expert-level support which can make customers’ life easier by reducing the overall design cycle and helping them bring their products to market faster.

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