tag: PAM4

PCIe Design Guide – Q&A (Gen 4, 5, 6) – Part 2
By Cadence - 23 Dec, 2025 - Comments: 0

As PCI Express (PCIe) evolves through Gen4, Gen5, and now Gen6, the complexity of high-speed design continues to grow. Signal and power integrity, equalization, clocking, and compliance — every layer of the PCB must be optimized for speed and reliability. The PCIe Design Guide – Q&A (Part 2) expands on the first volume with a deep dive into simulation, validation, and compliance, a... » read more

Designing for 448G: Modulation, DSP, and Channel Trade-offs in High-Speed SerDes
By Synopsys - 10 Dec, 2025 - Comments: 0

Discover practical solutions and engineering insights for deploying 448G SerDes in AI and HPC cluster networks. In this white paper, you’ll learn: The impact of retimed vs. unretimed host architectures on signal integrity and power Key trade-offs between PAM4 and PAM6 modulation Channel design simulations and DSP implications using real-world 448G topologies Equalization stra... » read more

Race to 448 Gbps
By Keysight - 06 Nov, 2025 - Comments: 0

The relentless growth in data center and AI workloads is accelerating the need for faster, more efficient interconnect technologies. As applications like large language models and distributed training infrastructures push the limits of bandwidth, 400/800G Ethernet is quickly becoming a bottleneck. To support next-generation performance at 1.6T and 3.2T system levels, engineers must enable relia... » read more

Programmable Hardware Delivers 10,000X Improvement In Verification Speed Over Software For Forward Error Correction
By Tony Chan Carusone - 28 Aug, 2025 - Comments: 0

In the race to increase the speeds of wireline networking and communications, forward error correction (FEC) has become a vital part of the toolkit. To function effectively, especially with the increasing use of four-level pulse amplitude modulation (PAM4), high-speed protocols need FEC to avoid a rise in the number of reception errors. Each incremental increase in the transmitted symbol rate r... » read more

Delivering Breakthrough Performance And Power Efficiency With PCIe 6
By Lou Ternullo - 10 Apr, 2025 - Comments: 0

PCI Express (PCIe) has been the backbone of high-speed data transfer in computing systems for nearly two decades. With each iteration, PCIe has not only increased data bandwidth but also introduced innovations aimed at enhancing power efficiency—a critical factor in today's energy-conscious computing environment. PCIe 6 introduced significant technical improvements that optimize power consump... » read more

PAM4: Pulse Amplitude Modulation Explained
By Ben Miller - 26 Sep, 2024 - Comments: 0

Pulse amplitude modulation (PAM) is already a widely adopted technology in high-speed digital communications. But to understand why it has become ubiquitous in serial data standards, you first must understand the market forces driving the data networking industry. In this article, I will explore PAM4 in-depth, from its benefits and potential tradeoffs to why it was an essential innovation that ... » read more

Essential Insights for Design PCIe 6.0 Interconnects
By Keysight - 24 Jul, 2024 - Comments: 0

PCI Express (PCIe) is a serial communication protocol that has progressed through generations to enhance data rates and functionality. The latest version, PCIe 6.0, doubles the data rate to 64 GT/s, enabling up to 256 GB/s of bandwidth in an x16 configuration. The technology incorporates PAM4 signaling and forward error correction to maintain high speeds with improved signal integrity and relia... » read more

Leveraging IBIS-AMI Models To Optimize PCIe 6.0 Designs
By Synopsys - 12 Dec, 2023 - Comments: 0

The exploding demand for more data driven by advancements such as artificial intelligence and machine learning has created an increase in bandwidth (BW) for interconnects for different systems and hardware components such as graphic cards, network cards, storge devices, CPUs, memories, and many more. PCIe is the leading high-speed serial communication protocol for connecting such hardware compo... » read more

DSP Techniques For High-Speed SerDes
By Ed Sperling - 23 Oct, 2023 - Comments: 0

Sensors everywhere, more connected devices, and the rollout of smart everything has created a flood of data. The question now is how to best handle all of that data, where to process it, and how to move it locally and to the outside network. Madhumita Sanyal, technical product manager at Synopsys, talks about the need for continuous performance improvements in SerDes, PCIe, NRZ, and PAM4, and w... » read more

Using A Retimer To Extend Reach For PCIe 6.0 Designs
By Lou Ternullo - 10 Aug, 2023 - Comments: 0

One of the biggest changes that came with PCIe 6.0 was the transition from non-return-to-zero (NRZ) signaling to PAM4 signaling. Pulse Amplitude Modulation (PAM) enables more bits to be transmitted at the same time on a serial channel. In PCIe 6.0, this translates to 2 bits per clock cycle for 4 amplitude levels (00, 01, 10, 11) vs. PCIe 5.0, and earlier generations, which used NRZ with 1 bit p... » read more

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