Using A Retimer To Extend Reach For PCIe 6.0 Designs

PAM4 signaling brings much higher data rates, but also new challenges in the design of the PCB and packages.


One of the biggest changes that came with PCIe 6.0 was the transition from non-return-to-zero (NRZ) signaling to PAM4 signaling. Pulse Amplitude Modulation (PAM) enables more bits to be transmitted at the same time on a serial channel. In PCIe 6.0, this translates to 2 bits per clock cycle for 4 amplitude levels (00, 01, 10, 11) vs. PCIe 5.0, and earlier generations, which used NRZ with 1 bit per clock cycle and two amplitude levels (0, 1). Essentially, PAM4 is what enables PCIe 6.0 to reach that new speed milestone of 64 gigatransfers per second (GT/sec), double that of the PCIe 5.0 standard.

But of course, there are always trade-offs. Given that we have now doubled the number of voltage levels, but don’t get to double our overall voltage budget, the transition to PAM4 signal encoding introduces a significantly higher Bit Error Rate (BER) vs. NRZ. This prompted the adoption of a new Forward Error Correction (FEC) mechanism in PCIe 6.0 to mitigate the higher error rate. The addition of a FLIT mode where packets are organized in flow control units of fixed sizes, as opposed to variable sizes in past PCIe generations, was also introduced as error correction requires fixed sized packets.

Now that we have set the scene, let’s dive into one of the big challenges that these new features translate to at a system design level. In terms of signal to noise reduction, we’re losing approximately 9 decibels (dB) of signal moving to PAM4. From an interval timing loss perspective, this equates to roughly a third. For pad-to-pad loss budget, the PCIe SIG has established 36 dB for PCIe 5.0 and 32 dB for PCIe 6.0 as targets. All this is calculated at the Nyquist frequency of 16 gigahertz (GHz).

The PCIe specification stipulates a root complex or CPU on a PCB, and it calls for approximately 12 to 14 inches of trace on the mother board and an additional 3-4 inches of trace on an add-in card equating to a total trace length of approximately 18 inches. These trace length targets are essentially the same for PCIe 5.0, as well as PCIe 6.0 systems. Designing a system to support the same trace length for PCIe 6.0 with the new PAM4 IO and higher data rate presents significant challenges in the design of the PCB and packages. Designing these boards with the same reach is going to have many implications, including tighter manufacturing tolerances, higher layer counts, etc. Also, as new distributed architectures are deployed in data centers, even greater flexibility is desired for chip placement, including the need for longer trace lengths.

One way to overcome these challenges and extend the overall reach is to use a retimer. A retimer captures and generates a new source signal. It is typically used to extend the physical reach of PCIe SerDes, including supporting the extension of a trace with riser cards or a backplane. Retimers can also be used to potentially reduce total system costs as you can avoid more costly PCB materials and manufacturing processes that are needed to reduce loss. Finally, retimers can give you some added confidence when it comes to different SerDes talking to each other. For example, a root complex to an add-in card from one vendor or an add-in card to a back plane from another vendor all operate differently. The total reach, as defined by the specification, may not be achievable reliably. A retimer can give you more possibilities from permutations and combinations of manufacturing tolerances and help you reduce overall design risk with a higher reliability solution with the potential of reducing BER of your complete system. A PCIe retimer offers another tool for PCIe system designers to help manage reliability and total system costs.

As PCIe data rates get faster and faster, and designs get increasingly complicated, it’s likely that we will see more use of retimers in PCIe designs. The Rambus PCIe 6.0 Retimer Controller IP provides a highly optimized low-latency data path for signal regeneration. It integrates with retimer chip PHYs via PIPE 5.2/6.1 interfaces. The PCIe 6.0 Retimer Controller is CXL protocol aware and supports links using 64 GT/s and lower data rates of PCIe.


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