Verifying Compliance During PCIe Re-Timer Testing Poses Challenges

By Kunal Chhabriya - 02 Nov, 2023 - Comments: 0

In PCI Express (PCIe), a high-speed serial computer expansion bus standard, Compliance mode is used for testing the transmitter and interconnect to assess if their voltage and timing are compliant with the specification. This testing happens in the Polling Compliance state which is a dedicated state for Compliance testing in the Link Training and Status State Machine (LTSSM). In Unraveling the... » read more

Using A Retimer To Extend Reach For PCIe 6.0 Designs

By Lou Ternullo - 10 Aug, 2023 - Comments: 0

One of the biggest changes that came with PCIe 6.0 was the transition from non-return-to-zero (NRZ) signaling to PAM4 signaling. Pulse Amplitude Modulation (PAM) enables more bits to be transmitted at the same time on a serial channel. In PCIe 6.0, this translates to 2 bits per clock cycle for 4 amplitude levels (00, 01, 10, 11) vs. PCIe 5.0, and earlier generations, which used NRZ with 1 bit p... » read more

Chipmakers Getting Serious About Integrated Photonics

By Brian Bailey - 12 Jul, 2021 - Comments: 3

Integrating photonics into semiconductors is gaining traction, particularly in heterogeneous multi-die packages, as chipmakers search for new ways to overcome power limitations and deal with increasing volumes of data. Power has been a growing concern since the end of Dennard scaling, which happened somewhere around the 90nm node. There are more transistors per mm², and the wires are thinne... » read more

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tag: retimer

Verifying Compliance During PCIe Re-Timer Testing Poses Challenges

Using A Retimer To Extend Reach For PCIe 6.0 Designs

Chipmakers Getting Serious About Integrated Photonics

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