tag: signaling

PCIe 8.0: Preparing For The Next Doubling
By Monica Olvera - 11 Dec, 2025 - Comments: 0

By Monica Olvera and Gustavo Pimentel Every few years, the industry confronts the same challenge: can general-purpose I/O double again without overwhelming power budgets, overwhelming signal-integrity limits, or fragmenting the ecosystem? With PCIe 8.0, the answer appears to be yes—if the entire stack continues to advance together. Public PCI-SIG information outlines an objective of 256.0 ... » read more

Designing for 448G: Modulation, DSP, and Channel Trade-offs in High-Speed SerDes
By Synopsys - 10 Dec, 2025 - Comments: 0

Discover practical solutions and engineering insights for deploying 448G SerDes in AI and HPC cluster networks. In this white paper, you’ll learn: The impact of retimed vs. unretimed host architectures on signal integrity and power Key trade-offs between PAM4 and PAM6 modulation Channel design simulations and DSP implications using real-world 448G topologies Equalization stra... » read more

Research Bits: Nov. 26
By Jesse Allen - 26 Nov, 2025 - Comments: 0

Hydrogel NAND gate Researchers from McMaster University and the University of Pittsburgh created a functionally complete NAND gate in a soft material using only beams of visible light. The NAND logic operation was completed by shining three self-trapped light beams into a photoresponsive merocyanine-functionalized hydrogel that is capable of performing compute tasks in the material itself w... » read more

Scaling AI Infrastructure: The Critical Role Of PCIe 7.0 Retimers
By Lou Ternullo - 13 Nov, 2025 - Comments: 0

In a previous blog, Scaling in the AI Era: The Role of PCI Express 7.0 Switches in Next-Gen Data Centers, we explored how PCIe 7.0 switches enable high-bandwidth, low-latency interconnects for AI-driven data centers. Switches are essential for building flexible, composable architectures that connect thousands of GPUs, accelerators, and memory subsystems. But as AI clusters grow in size and comp... » read more

Using A Retimer To Extend Reach For PCIe 6.0 Designs
By Lou Ternullo - 10 Aug, 2023 - Comments: 0

One of the biggest changes that came with PCIe 6.0 was the transition from non-return-to-zero (NRZ) signaling to PAM4 signaling. Pulse Amplitude Modulation (PAM) enables more bits to be transmitted at the same time on a serial channel. In PCIe 6.0, this translates to 2 bits per clock cycle for 4 amplitude levels (00, 01, 10, 11) vs. PCIe 5.0, and earlier generations, which used NRZ with 1 bit p... » read more

A Sea Change In Signaling With PCIe 6.0
By Tim Messegee - 12 May, 2022 - Comments: 0

PCI Express (PCIe) is one of those standards from the PC world, like Ethernet, that has proliferated far beyond its original application space. Thanks to its utility and economies of scale, PCIe has found a place in applications in IoT, automotive, test and measurement, medical, and more. As it has scaled, PCIe has pushed NRZ signaling to higher and higher levels reaching 32 gigatransfers per s... » read more

Choosing The Right Server Interface Architectures For High Performance Computing
By Jerry Lotto - 12 Apr, 2022 - Comments: 0

The largest bulk and cost of a modern high-performance computing (HPC) installation involves the acquisition or provisioning of many identical systems, interconnected by one or more networks, typically Ethernet and/or InfiniBand. Most HPC experts know that there are many choices between different server manufacturers and the options of form factor, CPU, RAM configuration, out of band management... » read more

Advancing Signaling Rates To 64 GT/s With PCI Express 6.0
By Tim Messegee - 13 Jan, 2022 - Comments: 0

From the introduction of PCI Express 3.0 (PCIe 3.0) in 2010 onward, each new generation of the standard has offered double the signaling rate of its predecessor. PCIe 3.0 saw a significant change to the protocol with the move from 8b/10b to highly efficient 128b/130b encoding. The PCIe 6.0 specification, now officially released, doubles the signaling rate to 64 gigatransfers per second (GT/s) a... » read more

CXL Signals A New Era Of Data Center Architecture
By Tim Messegee - 08 Jul, 2021 - Comments: 0

An exponential rise in data volume and traffic across the global internet infrastructure is motivating exploration of new architectures for the data center. Disaggregation and composability would move us beyond the classic architecture of the server as the unit of computing. By separating the functional components of compute, memory, storage and networking into pools, composed on-demand to matc... » read more

Striking the Right Chord for Chiplet Integration
By Kandou Bus - 14 Jan, 2019 - Comments: 0

The growing digitalization of our society has made our lives connected and, in many aspects, easier. But the digital revolution also implies that the total amount of data processed in the world is doubling every two years or so. Electronic devices such as mobile phones, laptops, satellites, servers or self-driving vehicles must cope with twice as much data, at higher speeds. Traditional signali... » read more

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