tag: PCIe

NOP Flit Payload: A Dedicated Debug Channel
By Geeta Arora - 24 Apr, 2025 - Comments: 0

Modern PCIe systems are complex, with high-speed data transfer and intricate protocols. Traditional debug methods often struggle to provide the necessary granularity and real-time visibility into link behavior. Transient issues, timing-sensitive errors, and protocol interactions can be difficult to pinpoint with conventional methodology. NOP Flit addresses this challenge. PCIe Gen 6 introduc... » read more

Delivering Breakthrough Performance And Power Efficiency With PCIe 6
By Lou Ternullo - 10 Apr, 2025 - Comments: 0

PCI Express (PCIe) has been the backbone of high-speed data transfer in computing systems for nearly two decades. With each iteration, PCIe has not only increased data bandwidth but also introduced innovations aimed at enhancing power efficiency—a critical factor in today's energy-conscious computing environment. PCIe 6 introduced significant technical improvements that optimize power consump... » read more

Secure Interfaces for Critical Semiconductor Applications
By Synopsys - 06 Mar, 2025 - Comments: 0

Security is now a concern for nearly all semiconductors in nearly all applications. Once of high interest mostly for military and financial systems, both the increasingly connected world and the plethora of existing security threats have changed the landscape dramatically. Every aspect of electronic system design—hardware, firmware, and software—has its own sets of risks and requirements to... » read more

Why HPC Chip Designers Are Looking Into Linear Pluggable Optics
By Synopsys - 12 Feb, 2025 - Comments: 0

This paper delves into the technical complexities and emerging trends in integrating linear pluggable optics within AI chip design. The rapid growth of hyperscale data centers, driven by the demands of LLMs and transformative AI applications, requires innovative solutions optimized for power, latency, and bandwidth. Emerging industry standards are ensuring interoperability between independently... » read more

Integrating Ethernet, PCIe, And UCIe For Enhanced Bandwidth And Scalability For AI/HPC Chips
By Madhumita Sanyal - 12 Dec, 2024 - Comments: 0

By Madhumita Sanyal and Aparna Tarde Multi-die architectures are becoming a pivotal solution for boosting performance, scalability, and adaptability in contemporary data centers. By breaking down traditional monolithic designs into smaller, either heterogeneous or homogeneous dies (also known as chiplets), engineers can fine-tune each component for specific functions, resulting in notable im... » read more

Why PCIe And CXL Are Essential Interconnects For The AI Era
By Lou Ternullo - 12 Dec, 2024 - Comments: 0

As the demand for AI and machine learning accelerates, the need for faster and more flexible data interconnects has never been more critical. Traditional data center architectures face several challenges in enabling efficient and scalable infrastructure to meet the needs of emerging AI use cases. The wide variety of AI use cases translate into different types of workloads. Some require high ... » read more

PCIe IP With Enhanced Security For The Automotive Market
By Dana Neustadter - 07 Nov, 2024 - Comments: 0

The automotive industry is undergoing a rapid transformation, with connectivity and automation becoming integral components of modern vehicles. However, this increased connectivity also brings heightened risks. The automotive industry takes many measures to ensure safety for vehicles, but it is crucial to understand that these safety measures are ineffective if the vehicle's security is comprom... » read more

Formally Modeling and Verifying CXL Cache Coherence (Imperial College London)
By Technical Paper Link - 22 Oct, 2024 - Comments: 0

A new technical paper titled "Formalising CXL Cache Coherence" was published by researchers at Imperial College London. Abstract "We report our experience formally modelling and verifying CXL.cache, the inter-device cache coherence protocol of the Compute Express Link standard. We have used the Isabelle proof assistant to create a formal model for CXL.cache based on the prose English spec... » read more

PIO on Current HW Outperforms DMA Over a Range of Payload Sizes In A Number of Different Applications (ETH Zurich)
By Technical Paper Link - 11 Oct, 2024 - Comments: 0

A new technical paper titled "Rethinking Programmed I/O for Fast Devices, Cheap Cores, and Coherent Interconnects" was published by researchers at ETH Zurich. Abstract: "Conventional wisdom holds that an efficient interface between an OS running on a CPU and a high-bandwidth I/O device should be based on Direct Memory Access (DMA), descriptor rings, and interrupts: DMA offloads transfers fr... » read more

Partial Header Encryption In Integrity And Data Encryption For PCIe
By Kunal Chhabriya - 10 Oct, 2024 - Comments: 0

Partial Header Encryption (PHE) is an additional mechanism added to Integrity and Data Encryption (IDE) in PCIe 6.0 to prevent side-channel attacks based on attacker analysis of the information included in the headers. This blog narrates PHE flow and Cadence VIP support for PHE in IDE across PCIe/CXL protocols. Background Introducing PCIe's Integrity and Data Encryption Feature is an excell... » read more

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