tag: PCIe

Beyond PCIe Compliance: Why Stress Testing Is Crucial For Edge AI Deployments
By Joe Chen - 04 Jun, 2026 - Comments: 0

Passing PCI Express (PCIe) compliance is different from being ready for the field. A PCIe link can clear every test in a controlled lab environment and still develop margin problems six months into deployment. That’s because a compliance traffic generator isn’t designed to replicate real-world operating conditions, such as thermal stress, electrical noise, and the kind of bursty inference t... » read more

Options Grow For Standardizing Data Movement And Sharing Resources
By Ed Sperling - 20 May, 2026 - Comments: 0

Semiconductor Engineering sat down to discuss memory interfaces, interconnects, and memory access scaling with Madhumita Sanyal, senior director of technical product management at Synopsys; Swadesh Choudhary, senior principal engineer at Intel; Siamak Tavallaei, senior principal engineer at Samsung SSI; and Mohsen Asad, senior director of technology at Credo. What follows are excerpts of a disc... » read more

Confusion Grows With More Interconnect Options And Tradeoffs
By Liz Allan - 18 May, 2026 - Comments: 0

Key Takeaways: Designers are frequently evaluating 5 or more different interconnects in a single system, each with a distinct purpose. While chip-to-chip (PCIe) and die-to-die (UCIe, BoW) technologies seem to be solving a similar problem, in practice they bring different challenges. PCIe, CXL, NVLink, and UALink are all active in the hyperscaler space, but Ethernet-based technologies... » read more

Scaling PCIe Controllers for AI Bandwidth: A Multistream Architecture Analysis for 64 GT/s and 128 GT/s
By Synopsys - 13 May, 2026 - Comments: 0

Scaling raw lane speed without rethinking controller microarchitecture leads to diminishing returns. It introduces multistream architecture, a controller‑level re‑architecture designed to sustain effective bandwidth under mixed and small‑packet workloads. This paper examines the architectural inflection point at PCIe 6.0, details transmit‑ and receive‑side changes required for multist... » read more

Chip Industry Week In Review
By The SE Staff - 08 May, 2026 - Comments: 0

Manufacturing ASE and WUS are jointly building a ~$1.1B advanced packaging hub in Kaohsiung, Taiwan, for fan-out chip-on-substrate (FOCoS) and flip-chip ball grid array (FC BGA) technologies. The new site is expected to be completed by September 2029. SpaceX filed documents for a “Terafab” semiconductor manufacturing and computing facility at Gibbons Creek Reservoir in Texas, with a... » read more

Unlocking High-Speed Serial Link Signal Integrity With AMI Model
By Priyadarshini N D - 30 Apr, 2026 - Comments: 0

As the demand for faster data rates in high-speed interfaces such as PCIe, USB, and DDR continues to escalate, maintaining signal integrity has become a significant challenge for engineers. Traditional SPICE-based simulations, while precise, often suffer from computational intensity, making it impractical to model the intricate behavior of high-speed signals across millions of bits. This is ... » read more

PCIe 8.0: Enabling The Next Generation Of High Bandwidth Systems
By Lou Ternullo - 09 Apr, 2026 - Comments: 0

As compute architectures evolve to support increasingly data‑intensive workloads, the role of high‑speed I/O has never been more critical. Artificial intelligence, high‑performance computing, hyperscale infrastructure, and advanced networking all depend on moving massive volumes of data efficiently, reliably, and at scale. The PCI‑SIG’s announcement of PCIe 8.0, which targets 256.0... » read more

PCIe Technology in Switches
By Rambus - 14 Jan, 2026 - Comments: 0

Two benefits of using PCIe switches include accessibility to more endpoints and enabling data center disaggregation. Rambus's Lou Ternullo and Wesley Yung from Astera Labs discuss benefits, use cases, and PCIe technology used in switches in this video from PCI-SIG. Hear more about the technology here. » read more

PCIe Design Guide – Q&A (Gen 4, 5, 6) – Part 2
By Cadence - 23 Dec, 2025 - Comments: 0

As PCI Express (PCIe) evolves through Gen4, Gen5, and now Gen6, the complexity of high-speed design continues to grow. Signal and power integrity, equalization, clocking, and compliance — every layer of the PCB must be optimized for speed and reliability. The PCIe Design Guide – Q&A (Part 2) expands on the first volume with a deep dive into simulation, validation, and compliance, a... » read more

PCIe 8.0: Preparing For The Next Doubling
By Monica Olvera - 11 Dec, 2025 - Comments: 0

By Monica Olvera and Gustavo Pimentel Every few years, the industry confronts the same challenge: can general-purpose I/O double again without overwhelming power budgets, overwhelming signal-integrity limits, or fragmenting the ecosystem? With PCIe 8.0, the answer appears to be yes—if the entire stack continues to advance together. Public PCI-SIG information outlines an objective of 256.0 ... » read more

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