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Compute Express Link (CXL): All You Need To Know


An in-depth look at Compute Express Link  (CXL) 2.0, an open standard cache-coherent interconnect between processors and accelerators, smart NICs, and memory devices. We explore how CXL is helping data centers more efficiently handle the yottabytes of data generated by artificial intelligence (AI) and machine learning (ML) applications. We discuss how CXL technology maintains memory c... » read more

PCIe 6.0, NVMe, And Emerging Form Factors For Storage Applications


PCIe 6.0 implementations are expandable and hierarchical with embedded switches or switch chips, allowing one root port to interface with multiple endpoints (such as storage devices, Ethernet cards, and display drivers). While the introduction of PCIe 6.0 at 64GT/s helped to increase the bandwidth available for storage applications with minimal or no increase in latency, the lack of coherency s... » read more

Data Security Drives Innovative Verification Capabilities For SoCs


The protection and integrity of data is a key challenge for organizations and businesses as human interactions with computers have expanded enormously. This has created a vast amount of information and led to the age of “Big Data” where massive, rich data sets are collected and analyzed to advance knowledge and progress in multiple fields. The security of this data has become a critical nee... » read more

Standardizing Chiplet Interconnects


The chip industry is making progress on standardizing the infrastructure for chiplets, setting the stage for faster and more predictable integration of different functions and features from different vendors. The ability to choose from a menu of small, highly specialized chips, and to mix and match them for specific applications and use cases, has been on the horizon for more than a decade. ... » read more

A Sea Change In Signaling With PCIe 6.0


PCI Express (PCIe) is one of those standards from the PC world, like Ethernet, that has proliferated far beyond its original application space. Thanks to its utility and economies of scale, PCIe has found a place in applications in IoT, automotive, test and measurement, medical, and more. As it has scaled, PCIe has pushed NRZ signaling to higher and higher levels reaching 32 gigatransfers per s... » read more

Choosing The Right Server Interface Architectures For High Performance Computing


The largest bulk and cost of a modern high-performance computing (HPC) installation involves the acquisition or provisioning of many identical systems, interconnected by one or more networks, typically Ethernet and/or InfiniBand. Most HPC experts know that there are many choices between different server manufacturers and the options of form factor, CPU, RAM configuration, out of band management... » read more

Improving Memory Efficiency And Performance


This is the second of two parts on CXL vs. OMI. Part one can be found here. Memory pooling and sharing are gaining traction as ways of optimizing existing resources to handle increasing data volumes. Using these approaches, memory can be accessed by a number of different machines or processing elements on an as-needed basis. Two protocols, CXL and OMI, are being leveraged to simplify thes... » read more

UCIe: Marketing Ruins It Again


You may have seen the press release and articles recently about a new standard called UCIe. It stands for Universal Chiplet Interconnect Express. The standard is a great idea and will certainly help the market for chiplet-based designs to advance. But the name — Argggh. More on that later. First, let's talk about what it is. You may notice the name looks similar to PCIe (Peripheral Compone... » read more

Chiplets Enter The Supercomputer Race


Several entities from various nations are racing each other to deliver and deploy chiplet-based exascale supercomputers, a new class of systems that are 1,000x faster than today’s supercomputers. The latest exascale supercomputer CPU and GPU designs mix and match complex dies in advanced packages, adding a new level of flexibility and customization for supercomputers. For years, various na... » read more

Leveraging Multi-Protocol PHY For PCIe To Cope With SoC Design Complexity


Now in the post-Moore’s Law era, the fast-evolving semiconductor market is continually geared toward higher performance and feature-rich integrated chip (IC) solutions. More functional design blocks integrated with growing interconnections—to not only increase the overall throughput but also expand the I/O connectivity—resulted in a more powerful system on chip (SoC). This increasing comp... » read more

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