tag: PCIe

PCIe Design Guide – Q&A (Gen 4, 5, 6) – Part 2
By Cadence - 23 Dec, 2025 - Comments: 0

As PCI Express (PCIe) evolves through Gen4, Gen5, and now Gen6, the complexity of high-speed design continues to grow. Signal and power integrity, equalization, clocking, and compliance — every layer of the PCB must be optimized for speed and reliability. The PCIe Design Guide – Q&A (Part 2) expands on the first volume with a deep dive into simulation, validation, and compliance, a... » read more

PCIe 8.0: Preparing For The Next Doubling
By Monica Olvera - 11 Dec, 2025 - Comments: 0

By Monica Olvera and Gustavo Pimentel Every few years, the industry confronts the same challenge: can general-purpose I/O double again without overwhelming power budgets, overwhelming signal-integrity limits, or fragmenting the ecosystem? With PCIe 8.0, the answer appears to be yes—if the entire stack continues to advance together. Public PCI-SIG information outlines an objective of 256.0 ... » read more

PCI Express Design Guide – Q&A for Gen 4, 5, 6
By Cadence - 24 Nov, 2025 - Comments: 0

High-speed PCB design for PCI Express Gen4, Gen5, and Gen6 pushes every dimension of signal integrity and layout engineering. This PCIe Design Guide – Q&A (Part 1) compiles 60 of the most common real-world design questions that engineers face—and provides detailed, practical answers grounded in simulation data, field experience, and compliance testing. Whether you’re defining your... » read more

Scaling AI Infrastructure: The Critical Role Of PCIe 7.0 Retimers
By Lou Ternullo - 13 Nov, 2025 - Comments: 0

In a previous blog, Scaling in the AI Era: The Role of PCI Express 7.0 Switches in Next-Gen Data Centers, we explored how PCIe 7.0 switches enable high-bandwidth, low-latency interconnects for AI-driven data centers. Switches are essential for building flexible, composable architectures that connect thousands of GPUs, accelerators, and memory subsystems. But as AI clusters grow in size and comp... » read more

PCIe Low-Power Validation Challenges And Potential Solutions
By Kunal Chhabriya - 13 Nov, 2025 - Comments: 0

As chip complexities increase and the industry evolves to more battery-powered devices, power-aware/consumption research becomes an integral part of design in the industry. Low power is crucial in ASIC applications to ensure longevity, durability, and reliability. PCI-SIG has focused on reducing power consumption while the PCIe interface is active to enable better platform power management (... » read more

Enhancing PCIe 6.0 Performance: Flit Sequence Numbers And Selective NAK Explained
By Felipe Gonçalves - 30 Oct, 2025 - Comments: 0

The Flit Sequence Number is a mechanism introduced in the PCIe 6.0 specification, accompanying the transition to Flit Mode operation. This enhancement supersedes the legacy transaction layer packet (TLP) sequence numbering, along with its associated acknowledgment and replay protocols. What is a Flit Sequence Number? Historically, each TLP carried an explicit sequence number, which, while con... » read more

Rethinking AI Infrastructure: The Rise Of PCIe Switches
By Vanessa Do - 11 Sep, 2025 - Comments: 0

When thinking of AI, images of futuristic robots or self-driving cars may come to mind. What might not come to mind are the unsung hardware component heroes that are quietly enabling such complex systems. Among these, PCI Express (PCIe) switches might seem to be a boring topic to write about, much less read. But here's the twist—they are nothing short of revolutionary when it comes to empower... » read more

An Overview Of CXL Mode Alternate Protocol Negotiation
By Guo Yu - 28 Aug, 2025 - Comments: 0

The Peripheral Component Interconnect Express (PCIe) protocol has a very powerful feature called Alternate Protocol Negotiation (APN), which was introduced in the PCIe 5.0 specification. This feature allows the alternate protocols (non-PCIe) that use PCIe PHY layer to be enabled and provide their own implementation of the more abstract layers. One of the most common alternate protocols is th... » read more

Scalable I/O Virtualization: A Deep Dive Into PCIe’s Next Gen Virtualization
By Geeta Arora - 07 Aug, 2025 - Comments: 0

The demands of modern cloud computing—massive scale, constant agility, and tight security—are pushing traditional I/O virtualization to its limits. While SR-IOV (Single Root I/O Virtualization) was a foundational technology, it wasn't built for the high-density, multi-tenant environments common today. To meet this challenge, the PCIe specification has evolved with Scalable I/O Virtualiza... » read more

Scaling In The AI Era: The Role Of PCI Express 7.0 Switches In Next-Gen Data Centers
By Lou Ternullo - 17 Jul, 2025 - Comments: 0

As artificial intelligence (AI) workloads continue to scale in complexity and volume, the infrastructure that supports them must evolve just as rapidly. At the heart of this transformation lies PCI Express 7.0 (PCIe 7.0), a next-generation interconnect standard that is redefining how data moves within high-performance computing (HPC) and AI-driven data centers. PCIe 7.0 doubles the raw bit r... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy