tag: PAM4

Evolution Of Equalization Techniques In High-Speed SerDes For Extended Reaches
By Madhumita Sanyal - 20 Jul, 2023 - Comments: 0

The relentless demand for massive amounts of data is accelerating the pace of high-performance computing (HPC) within the high-speed Ethernet realm. This escalation, in turn, intensified the complexity associated with designing networking SoCs, including switches, NICs, retimers, and pluggable modules. Such growth is accelerating the demand for bandwidth hungry applications to transition from 4... » read more

Advanced Modulation And Coding Challenges
By Keysight - 22 Feb, 2023 - Comments: 0

Demands for a connected world with instant data access continue to drive data center transceiver innovation. 100 gigabit Ethernet (GE) data transmission is in production and will continue to evolve. But 100GE speeds aren’t fast enough to support the expected surge in connected devices and the applications they will run, opening the door for 400GE. Non-return-to-zero (NRZ) and four-level pulse... » read more

PCIe 6.0 Takes Data Center Performance To The Next Level
By Lou Ternullo - 12 Jan, 2023 - Comments: 0

Looking back at 2022, we saw a major update to the PCI Express (PCIe) specification. PCIe 6.0 brought with it some of the most fundamental changes yet seen by the specification, resulting in some exciting capabilities that are set to take data center performance to the next level in the years ahead. PCIe has been the interconnect of choice in computing for two decades now. Its ongoing advanc... » read more

Chip Sandwich: Electronics Chip & Photonics Chip Co-Optimized To Work Together (CalTech/Univ. of Southampton)
By Technical Paper Link - 01 Dec, 2022 - Comments: 0

A technical paper titled "A 100-Gb/s PAM4 Optical Transmitter in a 3-D-Integrated SiPh-CMOS Platform Using Segmented MOSCAP Modulators" was published by researchers at CalTech and University of Southampton. "The resulting optimized interface between the two chips allows them to transmit 100 gigabits of data per second while producing just 2.4 pico-Joules per transmitted bit. This improves th... » read more

A Sea Change In Signaling With PCIe 6.0
By Tim Messegee - 12 May, 2022 - Comments: 0

PCI Express (PCIe) is one of those standards from the PC world, like Ethernet, that has proliferated far beyond its original application space. Thanks to its utility and economies of scale, PCIe has found a place in applications in IoT, automotive, test and measurement, medical, and more. As it has scaled, PCIe has pushed NRZ signaling to higher and higher levels reaching 32 gigatransfers per s... » read more

Choosing The Right Server Interface Architectures For High Performance Computing
By Jerry Lotto - 12 Apr, 2022 - Comments: 0

The largest bulk and cost of a modern high-performance computing (HPC) installation involves the acquisition or provisioning of many identical systems, interconnected by one or more networks, typically Ethernet and/or InfiniBand. Most HPC experts know that there are many choices between different server manufacturers and the options of form factor, CPU, RAM configuration, out of band management... » read more

Advancing Signaling Rates To 64 GT/s With PCI Express 6.0
By Tim Messegee - 13 Jan, 2022 - Comments: 0

From the introduction of PCI Express 3.0 (PCIe 3.0) in 2010 onward, each new generation of the standard has offered double the signaling rate of its predecessor. PCIe 3.0 saw a significant change to the protocol with the move from 8b/10b to highly efficient 128b/130b encoding. The PCIe 6.0 specification, now officially released, doubles the signaling rate to 64 gigatransfers per second (GT/s) a... » read more

CXL Signals A New Era Of Data Center Architecture
By Tim Messegee - 08 Jul, 2021 - Comments: 0

An exponential rise in data volume and traffic across the global internet infrastructure is motivating exploration of new architectures for the data center. Disaggregation and composability would move us beyond the classic architecture of the server as the unit of computing. By separating the functional components of compute, memory, storage and networking into pools, composed on-demand to matc... » read more

Re-Architecting SerDes
By Brian Bailey - 10 Dec, 2020 - Comments: 0

Serializer/Deserializer (SerDes) circuits have been helping semiconductors move data around for years, but new process technologies are forcing it to adapt and change in unexpected ways. Traditionally implemented as an analog circuit, SerDes technology has been difficult to scale, while low voltages, variation, and noise are making it more difficult to yield sufficiently. So to remain releva... » read more

Enabling Cost-Effective, High-Performance Die-to-Die Connectivity
By Thomas Wong - 09 Jul, 2020 - Comments: 0

System advances in accelerated computing platforms such as CPUs, GPUs and FPGAs, heterogeneous systems on chip (SoCs) for AI acceleration and high-speed networking/interconnects have all pushed chip integration to unprecedented levels. This requires more complex designs and higher levels of integration, larger die sizes and adopting the most advanced geometries as quickly as possible. Facing th... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy