A Review Of Acoustic Side-Channel Attacks: An AI View (Penn State Univ.)


A new technical paper titled "A Survey on Acoustic Side-Channel Attacks: An Artificial Intelligence Perspective" was published by researchers at Penn State University. Abstract "Acoustic Side-Channel Attacks (ASCAs) exploit the sound produced by keyboards and other devices to infer sensitive information without breaching software or network defenses. Recent advances in deep learning, large ... » read more

Research Bits: July 29


Sort-in-memory Researchers from Peking University and the Chinese Institute for Brain Research developed a sort-in-memory hardware system based on memristors that is tailored for complex, nonlinear sorting tasks. The comparator-free processing-in-memory architecture is built on a one-transistor–one-resistor (1T1R) memristor array, using a Digit Read mechanism that replaces traditional com... » read more

Research Bits: May 13


Benchmarking 3D-IC cooling Researchers from Massachusetts Institute of Technology (MIT) and HRL Laboratories developed a specialized chip to test and validate cooling solutions for packaged chip stacks. The chip dissipates extremely high power, generating heat through the silicon layer and in localized hot spots to mimic high-performance logic chips. It then uses diodes to measure temperatu... » read more

Accelerate Complex Algorithms With Adaptable Signal Processing Solutions


Technology is continuously advancing and exponentially increasing the amount of data produced. Data comes from a multitude of sources and formats, requiring systems to process different algorithms. Each of these algorithms present their own challenges including low-latency and deterministic processing to keep up with incoming data rates and rapid response time. Considering that many of these se... » read more

A Survey Of Recent Advances In Spiking Neural Networks From Algorithms To HW Acceleration


A technical paper titled “Recent Advances in Scalable Energy-Efficient and Trustworthy Spiking Neural networks: from Algorithms to Technology” was published by researchers at Intel Labs, University of California Santa Cruz, University of Wisconsin-Madison, and University of Southern California. Abstract: "Neuromorphic computing and, in particular, spiking neural networks (SNNs) have becom... » read more

Evolution Of Equalization Techniques In High-Speed SerDes For Extended Reaches


The relentless demand for massive amounts of data is accelerating the pace of high-performance computing (HPC) within the high-speed Ethernet realm. This escalation, in turn, intensified the complexity associated with designing networking SoCs, including switches, NICs, retimers, and pluggable modules. Such growth is accelerating the demand for bandwidth hungry applications to transition from 4... » read more

Improved DSP And AI Performance On An MCU Core


In the world of embedded devices, there's a growing demand for advanced machine learning and signal processing capabilities. ARM Cortex-M85, the latest general-purpose core, aims to meet these demands with its 32-bit Armv8.1-M architecture, offering high performance and power efficiency. The core's Helium technology, M-profile vector extension (MVE), provides significant uplift for ML/DSP appl... » read more

Advances In Reconfigurable Intelligent Surfaces Hardware Architectures: Beyond 5G/6G


This technical paper titled "Reconfigurable Intelligent Surfaces for Wireless Communications: Overview of Hardware Designs, Channel Models, and Estimation Techniques" is from researchers at IEEE. The paper's abstract states "we overview and taxonomize the latest advances in RIS [reconfigurable intelligent surfaces] hardware architectures as well as the most recent developments in the modelin... » read more

The speed limit of optoelectronics


Abstract "Light-field driven charge motion links semiconductor technology to electric fields with attosecond temporal control. Motivated by ultimate-speed electron-based signal processing, strong-field excitation has been identified viable for the ultrafast manipulation of a solid’s electronic properties but found to evoke perplexing post-excitation dynamics. Here, we report on single-photon... » read more

Improving Performance And Simplifying Coding With XY Memory’s Implicit Parallelism


Instruction-level Parallelism (ILP) refers to design techniques that enable more than one RISC instruction to be executed simultaneously in the same instruction, which boosts processor performance by increasing the amount of work done in a given time interval, thereby increasing the throughput. This parallelism can be explicit, where each additional instruction is explicitly part of the instruc... » read more

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