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Improving Performance And Simplifying Coding With XY Memory’s Implicit Parallelism

Adding the power of a digital signal processing engine to DesignWare ARC configurable processor cores to enable RISC and signal processing computation within a single unified architecture.

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Instruction-level Parallelism (ILP) refers to design techniques that enable more than one RISC instruction to be executed simultaneously in the same instruction, which boosts processor performance by increasing the amount of work done in a given time interval, thereby increasing the throughput. This parallelism can be explicit, where each additional instruction is explicitly part of the instruction mnemonic, or it can be implicit, where the number and type of operations are encoded into the instruction. Implicit instruction parallelism using XY memory retains the RISC programming model and brings all the XY memories into the pipeline as if they were register files, resulting in a resource-efficient and a much higher performing implementation. The DesignWare  ARC XY Advanced DSP extension adds the power of a digital signal processing engine to DesignWare ARC configurable processor cores, enabling RISC and signal processing computation within a single unified architecture.

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