In-Design Power Rail Analysis


Tech Talk: Kenneth Chang, senior staff product marketing manager at Synopsys, talks about what can go wrong with power at advanced nodes and why in-design power rail analysis works best early in the flow in helping to reduce overall margin. https://youtu.be/0oiWQPS1-Xk » read more

A High-Speed Asynchronous Multi-Input Pipeline For Compaction And Transfer of Parallel SIMD Data


Image sensors with programmable, highly parallel signal processing, so called Vision-Systems-on-Chip, perform computationally intensive tasks directly on the sensor itself. Therefore it is possible to limit the amount of output data to relevant image features only. Reading out such features presents a major challenge, since the position and number of features often is not known. Conventional sy... » read more

Right-Sizing Your Cryptographic Processing Solution


The cornerstone of all security solutions that deal with confidentiality, integrity and authentication is cryptography. Cryptography is a complex math problem used to help create security applications. Algorithms vary for different applications and are used for specific purposes. The common cryptographic algorithms are symmetric block ciphers for confidentiality, hash functions for integrity, a... » read more

Understanding The Effect Of Variability In Bulk FinFET Device Performance


2-D MOSFETs have proven difficult to scale down to 20nm and beyond. In their place, 3D FinFET transistors have emerged as novel devices that can scale down to lower node sizes. 10nm process finFETs are for SoC product mass production, and research is progressing towards a 7nm process finFET. FinFET transistors provide lower dynamic power consumption (due to flatter I-V curves), improved control... » read more

Measuring And Analyzing SoC Performance With Verdi Performance Analyzer


SoC performance is a key competitive advantage in the marketplace. The choice and configuration of SoC components—protocol IP and interconnects, is geared towards maximizing overall SoC performance. A case in point is the use of HBM (High Bandwidth Memory) technology and controllers. Currently in its third generation, HBM boasts high-performance while using less power in a substantially small... » read more

Digital Twins: Making The Vision Achievable


Few business concepts are generating the buzz of digital twins — product replicas that can help target performance issues and allow for true predictive maintenance. While the benefits are obvious, companies have struggled with how to achieve this vision. But now there is a practical solution. To read more, click here. » read more

Why All Nodes Won’t Work


A flood of new nodes, half-nodes and every number in between is creating confusion among chipmakers. While most say it's good to have choices, it's not clear which or how many of those choices are actually good. At issue is which [getkc id="43" kc_name="IP"] will be available for those nodes, how that IP will differ from other nodes in terms of power, performance, area and sensitivity to a v... » read more

Zen And The Art Of Network Timestamping


Network devices, namely switches and routers, are used for forwarding data packets from their source to their destination - or at least that is what they are meant to do. In practice, these devices tend to do a lot more than that. They can be involved in Quality of Service (QoS) enforcement, filtering, load balancing, fault detection, performance measurement, event logging and various other act... » read more

Pushing Performance Limits


Trying to squeeze the last bit of performance out of a chip sounds like a good idea, but it increases risk and cost, extends development time, reduced yield, and it may even limit the environments in which the chip can operate. And yet, given the amount of margin added at every step of the development process, it seems obvious that plenty of improvements could be made. "Every design can be o... » read more

7/5nm Timing Closure Intensifies


Timing closure issues are increasing in magnitude at 7/5nm, and ones that were often considered minor in the past no longer can be ignored. Timing closure is an essential part of any chip design. The process ensures that all combinatorial paths through a design meet the necessary timing so that it can run reliably at a specified clock rate. Timing closure hasn't changed significantly over th... » read more

← Older posts