Dual Instruction-Set Architecture, Supporting A TTA And RISC-V Instruction Set Via a Lightweight Microcode Hardware Unit

A technical paper titled “Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode” was published by researchers at Tampere University. Abstract: "Transport triggered architectures (TTAs) follow the static programming model of very long instruction word (VLIW) processors but expose additional information of the processor datapath in the programming interface, whic... » read more

Improving Performance And Simplifying Coding With XY Memory’s Implicit Parallelism

Instruction-level Parallelism (ILP) refers to design techniques that enable more than one RISC instruction to be executed simultaneously in the same instruction, which boosts processor performance by increasing the amount of work done in a given time interval, thereby increasing the throughput. This parallelism can be explicit, where each additional instruction is explicitly part of the instruc... » read more