tag: forward error correction

Latency Considerations For 1.6T Ethernet Designs
By Jon Ames - 12 Oct, 2023 - Comments: 0

Since its 1980s debut with 10Mbps shared LANs over coaxial cables, Ethernet has seen consistent advancements, now with the potential to support speeds up to 1.6Tbps. This progression has allowed Ethernet to serve a wider range of applications, such as live streaming, Radio Access Networks and industrial control, emphasizing the importance of reliable packet transfer and quality of service. With... » read more

Evolution Of Equalization Techniques In High-Speed SerDes For Extended Reaches
By Madhumita Sanyal - 20 Jul, 2023 - Comments: 0

The relentless demand for massive amounts of data is accelerating the pace of high-performance computing (HPC) within the high-speed Ethernet realm. This escalation, in turn, intensified the complexity associated with designing networking SoCs, including switches, NICs, retimers, and pluggable modules. Such growth is accelerating the demand for bandwidth hungry applications to transition from 4... » read more

Breaking The 1M RAID5 Write IOPS Barrier
By Samsung - 17 May, 2023 - Comments: 0

In today’s data-centric age, enormous amounts of data are generated, stored and processed at an unprecedented rate. Businesses are utilizing this data to make better decisions, drive greater efficiencies, develop more desirable products, improve profitability and ultimately increase user satisfaction. To continue deriving a high degree of value from a rapidly-expanding data flow, today’s en... » read more

PCIe 6.0 Electrical Testing For High Data-Bandwidth Applications
By Cadence - 22 Mar, 2023 - Comments: 0

For nearly three decades, PCI Express (PCIe) technology has been the standard interconnect inside computers providing high bandwidth and low latency to meet customer demand. However, as the industry needs to evolve, so does the standard, keeping pace and driving future innovation. PCIe 6.0 is ubiquitous and offers power-efficient performance and high bandwidth for latency-sensitive applicati... » read more

Video Compression And Forward Error Correction On Display Interfaces
By Emma-Jane Crozier - 13 Sep, 2022 - Comments: 0

To wrap up our recent series of articles on VESA video compression codecs, this month we will look at the use of video compression on digital display interfaces, using the DisplayPort 1.4 standard as an example. DisplayPort (DP) 1.4 was released in 2016, and this was the first display interface standard for external displays to include support for VESA Display Stream Compression (DSC), a vis... » read more

A Sea Change In Signaling With PCIe 6.0
By Tim Messegee - 12 May, 2022 - Comments: 0

PCI Express (PCIe) is one of those standards from the PC world, like Ethernet, that has proliferated far beyond its original application space. Thanks to its utility and economies of scale, PCIe has found a place in applications in IoT, automotive, test and measurement, medical, and more. As it has scaled, PCIe has pushed NRZ signaling to higher and higher levels reaching 32 gigatransfers per s... » read more

Reservoir Computing based on Mutually Injected Phase Modulated Semiconductor Lasers as a Monolithic Integrated Hardware Accelerator
By Technical Paper Link - 08 Feb, 2022 - Comments: 0

Abstract: "In this paper we propose and numerically study a neuromorphic computing scheme that applies delay-based reservoir computing in a laser system consisting of two mutually coupled phase modulated lasers. The scheme can be monolithic integrated in a straightforward manner and alleviates the need for external optical injection, as the data can be directly applied on the on-chip phase m... » read more

Getting Ready For An Efficient Shift To PCI Express 6.0 Designs With Optimized IP
By Gary Ruggles - 10 Jun, 2021 - Comments: 0

PCI Express (PCIe) 6.0 technology with key changes will bring about challenges that high-performance computing, artificial intelligence, and storage system-on-chip (SoC) designers will face. This article provides designers a summary of the major changes and how they can be handled to ensure a smooth and successful transition to PCIe 6.0. The three major changes in PCIe 6.0 that designers nee... » read more

SerDes For Chiplets
By Jeff McGuire - 16 Oct, 2018 - Comments: 0

The XSR 56G and 112G Interoperability Agreements (IAs) announced by the OIF are intended to cover a channel consisting of a pair of up to 50mm. The primary defined application of the XSR SerDes is connecting a chip to a “nearby” optical engine. Because the requirements on these channels are much less stringent than they are on long reach channels, XSR SerDes are expected to have lower power... » read more

A Dual-Mode Error-Correcting Code Solution For 50Gbps Ethernet
By Synopsys - 25 Oct, 2017 - Comments: 0

The increase in bandwidth is driving more innovations in the Ethernet physical layer technology to combat numerous challenges like channel loss, inter-symbol interference and more importantly error detection and correction. It is imperative to have a mechanism in place to detect and correct errors as data is transmitted and received, while maintaining small silicon area and low power consumptio... » read more

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