中文 English

Getting Ready For An Efficient Shift To PCI Express 6.0 Designs With Optimized IP


PCI Express (PCIe) 6.0 technology with key changes will bring about challenges that high-performance computing, artificial intelligence, and storage system-on-chip (SoC) designers will face. This article provides designers a summary of the major changes and how they can be handled to ensure a smooth and successful transition to PCIe 6.0. The three major changes in PCIe 6.0 that designers nee... » read more

SerDes For Chiplets


The XSR 56G and 112G Interoperability Agreements (IAs) announced by the OIF are intended to cover a channel consisting of a pair of up to 50mm. The primary defined application of the XSR SerDes is connecting a chip to a “nearby” optical engine. Because the requirements on these channels are much less stringent than they are on long reach channels, XSR SerDes are expected to have lower power... » read more

A Dual-Mode Error-Correcting Code Solution For 50Gbps Ethernet


The increase in bandwidth is driving more innovations in the Ethernet physical layer technology to combat numerous challenges like channel loss, inter-symbol interference and more importantly error detection and correction. It is imperative to have a mechanism in place to detect and correct errors as data is transmitted and received, while maintaining small silicon area and low power consumptio... » read more