Designing 2.5D Systems

Connecting dies using an interposer requires new and modified processes, as well as organizational changes.


As more designs hit the reticle limit, or suffer from decreasing yield, migrating to 2.5D designs may provide a path forward. But this kind of advanced packaging also comes with some additional challenges.

How you adapt and change your design team may be determined by where your focus has been in the past, or what you are trying to achieve. There are business, organizational, and technical challenges.

At first glance, 2.5D design — or what some people call heterogeneous integration — is like a tiny PCB implemented in silicon. Components are placed onto that base layer, and then assembled into a package. And this is where the first big distinction comes from. Are you trying to migrate from a PCB or MCM world into 2.5D design, are you trying to split a single-die SoC into multiple pieces? And is the objective to pack more functionality into a package, or is it like the DARPA approach, where you are trying to speed up and lower the cost of the design process by being using pre-designed and pre-verified chiplets?

The starting point defines the amount of change you will face and the potential pitfalls along the way. Part one of this series examined the general state of the industry based on how this packaging approach is being used by early adopters. The focus here is on some of the changes in the development flow.

What causes difficulty is that two teams are being brought together, the ASIC team and the packaging team, and the responsibilities between them is being altered. “Traditionally, the silicon and the package design environments, and the associated engineering expertise and tools have been separated,” says Anna Fontanelli, founder and CEO of Monozukuri. “IC design is done on Unix workstations, package design on Windows PC. The package is designed like a commodity at the end of a completely independent silicon design flow. Now, teams are forced to move to a fully integrated chiplet-plus-package and surrounding PCB design flow, which takes in account the complexity of the interconnect while working in a 3D design space.”

The cultures of those two groups are different. “If we think back to a system at the PCB level or the MCM level, the design of those, at least as far as the manufacturers are concerned, was pretty loose,” says Chris Ortiz, principal application engineer at Ansys. “They don’t have strict design rules. On the chip side, they have very strict design rules. There’s going to be a lot of design rules they have to adhere to in a 2.5D flow. That will limit the danger of doing something wrong compared to the past, but they’re still going to need to look at things and analyze them like in the chip world.”

Design teams coming from the ASIC/SoC world probably have the least number of changes. “The ASIC flows are pretty mature, and they haven’t changed significantly,” says Tony Mastroianni, advanced packaging solutions director for Siemens EDA. “The difference is that more collaboration is required between the ASIC design teams and the package design teams, just to get everything to interface to each other. Interconnect within the package has traditionally been done by the physical design team, but for silicon interposers it is predominantly owned by the ASIC teams. There will need to be quite a bit of collaboration that happens with the package team.”

Those coming from the packaging side likely will see bigger changes. “A traditional package designer probably has a tool that’s suitable for laminate-style packaging — BGA-style design tools,” says John Park, product management group director for IC packaging and cross-platform solutions at Cadence. “When they transition from that to designing something on silicon, the first thing that changes is they are outputting GDS data instead of Gerber data. They are no longer going to board manufacturing houses. They are going to a silicon fab. As soon as you make that transition to outputting GDS, you also then have to add sign-off to your flow. People don’t typically build things out of silicon unless they’re known to be DRC-clean, LVS-clean. There are more requirements for things like metal fill.”

Team skills may change, too. “Larger companies probably have the skill sets they need, but they probably have not worked together,” says Siemens’ Mastroianni. “They will need to work together, so whether or not they restructure the organization to have those capabilities — or they just realize that they can’t just have silos working independently, where they hand pieces over the wall — they need a collaborative design environment.”

An evolving flow
There is no single flow the industry has standardized on, and it’s unlikely that will change anytime soon because the field is rapidly evolving.

Today, the focus is primarily on passive silicon interposers, but the future may well have active interposers or 3D stacking, which will have significant impact. “Passive silicon interposers are just metal, typically three or four metal layers, so you’re just connecting things together using metal routing,” says Cadence’s Park. “You’re not inserting buffers or creating logic. It is closely associated with how we do system-in-package (SiP), or multi-chip module (MCM), where you are working with bare die and connecting those together. In the case of a silicon interposer, most of the chiplets will have micro buffers, so they’ll be similar to full chips, and they will have their own test, etc. For the next couple of years, at least, the approach will be similar to MCM, SiP.”

Adding functionality to the interposer will magnify some of the changes required. “For a passive interposer, it’s simply a routing problem,” says Mastroianni. “It’s not a place-and-route problem. Initially, you’ll see some simple things like buffering. When you have long traces, you can only go so far die-to-die. Then you have to worry about placing buffers for longer signals, particularly for things like test signals. Then you’ll have to start using place-and-route tools, and that’s going to require more of the ASIC flow. They will need to utilize timing-driven placement, and static timing analysis between the dies. A lot of the design and verification functions that were limited to the ASIC world will now get dragged into the whole package.”

Some of the problems result from complexity, while others are related to physics. “Interposer manufacture requires modifications to both processes and materials,” says Mark O’Neill, R&D head of semiconductor solutions with EMD Electronics, a business of Merck KGaA, Darmstadt, Germany. “It also poses additional challenges that have not been experienced in 2D chip manufacturing. This includes large, high-aspect-ratio through-substrate vias, high polish rate/uniquely selective CMP slurries, and the impacts of materials properties at larger size scales than in standard interconnects, such as CTE (coefficient of thermal expansion) mismatch, adhesion and interfacial stresses. New materials are required to address these challenges, and innovations in materials is key for advances in packaging integration to provide reliability of performance.”

There are several areas of the flow that are impacted — architectural exploration and planning, design and implementation of the chiplets and interposer, integration and verification of the system at both the functional and physical levels, and sign-off.

This is adding some steps and modifying others. Figure 1 shows an evolution of the issues that have been added to the design flow over time.

Fig. 1: Additional concerns incorporated into chip design. Source: Cadence

Architectural partitioning
Mistakes can be made when partitioning functionality. “The use of any sort of interconnect means that a natural division point must be found within the chip that is to be sub-divided,” says Brian Holden, vice president of standards at Kandou. “That division must be such that significant circuitry is located on each of the chiplets in order to achieve a gain from dividing the larger chip into chiplets. Separating the chip into tiles allows different versions of the solution to be made with differing counts of tile chiplets. A classic design problem with tile solutions is to design an efficient communication system to handle connections between tiles that are not directly attached to each other. Many solutions to this problem have been developed over the years, and include router fabrics and torus networks.”

But that is just one piece of the puzzle. “Just like a 2D design, early floor planning has to be done and the architect needs to be aware of what’s coming downstream,” says Vinay Patwardhan, senior director, product management at Cadence. “While doing the partitioning and floor planning, they need to be aware of not just the downstream effects from 2D wires, but also 3D structures like TSVs. What restrictions and rules will they have in placement? What restrictions are imposed by the chiplets they are integrating, or the interconnect standards they are using? Based on those, they may have to adjust the floor plan or partitioning. It can be hard enough to iterate for a single 2D chip or an SoC, but imagine if we are talking about IPs at 7nm being assembled on an interposer? You will get more efficient convergence if you are aware of downstream physical things much earlier in the flow.”

Companies may not find all of the necessary skills in one person, however. “People from many disciplines will have to be working together,” says Kenneth Larsen, director of product marketing for Synopsys. “In some cases, that will include internal packaging guys, the ASIC team, thermal and signal integrity (SI) and power integrity (PI) folks, DFT, static timing, and then obviously the systems architect. Some of the challenges, and some of the areas of improvement to the old workflow, are really about collaboration across these disciplines. It is no longer just one guy figuring everything out. It’s more of an iterative and collaborative environment.”

They need a common way to communicate. “Tradeoff studies need to be done to come up with the correct placements for each die, or chiplets within the die, or connecting to different dies from one die,” says Sooyong Kim, director and product specialist in 3D-IC chip package systems and multiphysics at Ansys. “What are the interfaces? How many bumps? How many TSVs? What are the densities of those TSVs? How many layers are appropriate for making those interfaces, in terms of SI impact, in terms of PI impact, or in terms of mechanical impact? They don’t have the full details at this stage, but they need to be able to accurately come up with something called a prototyping flow. They need to be able to make 70% of the decisions for the planning stage. This planning should remain coherent all the way to the sign-off.”

While it may require a team to do this, that team still needs a leader. “Early feasibility and architectural studies avoid potential disastrous configurations that could result in significant time being wasted on designs that will go nowhere,” says Monozukuri’s Fontanelli. “A new profile of engineer should lead and supervise the system design activity from the early stages. This should be someone who understand the design targets, has a complete picture for the final electronic product, and owns the constraints needed to reach the expected product performance.”

This will place additional requirements on things like modeling. “Teams have to start using higher-level models and add details as they go,” says Mastroianni. “For example, once you have an initial place-and-route, you can start doing more detailed power analysis, and more detailed thermal analysis. This happens throughout the process. With the interposer, some of that has to wait until the layout for the ASICs firm up, and then you start doing micro-bump planning. That’s something where there is quite a bit of collaboration that needs to happen to get synchronized.”

New models may be required, too. “As more functionality gets added, there will be a growing need for each piece to have multiple representations — and by multiple representations I mean multiple levels of abstraction,” says Cadence’s Patwardhan. “That includes what is inside each IP, and also the view from outside the IP, which will be needed by the system-level integration folks. If they can get an early view of what is coming on the interposers, in the same view, the same database, it will shorten the whole implementation loop. Basically, they’re fuzzing the boundaries by using boundary models or interface models.”

Help also may come from unexpected places. “Traditionally, the foundries haven’t been active in the packaging area, but now, seeing that the substrates are silicon too, they see a bigger role for themselves,” says Marc Swinnen, director of product marketing at Ansys. “When you look at the CoWoS and InFO structures from TSMC, for example, they have now come up with a set of pre-packaged suggested floor plans. These have been pre-characterized. They have been run through the design flows. It simplifies a lot of the options for a team starting out on this journey. The foundries will be playing a bigger role in guiding and suggesting how these implementations should be done.”

Functional verification traditionally has followed the V diagram, where after a partitioning phase, each piece is independently implemented and verified and then an integration with verification phase takes place to bring the pieces back together. “2.5D integration results in more complex verification strategies and practices, and a greater number of connectivity issues that need to be identified and solved,” says Vladislav Palfy, director of application engineering for OneSpin Solutions. “Verification must be tackled earlier in the process at the block level. Doing this will minimize the risk of bug escapes later that become more critical and harder to detect. It’s important to note that verifying expected behavior is not enough. For a design to be fully verified, making sure the absence of particular behaviors is required. To that end, it should also be pointed out that as these blocks get verified, the understanding of verification coverage also becomes essential. Precise metrics are needed to understand if the design from the block-level to the full SoC has been completely verified. Formal is the only method for ensuring the sanctity of connectivity, the possibility of proving absence of scenarios, as well as making sure coverage goals are met.”

Even for physical verification, the industry agrees that you cannot wait until the end. “There are too many things that could go wrong if you just wait to the end where everything comes together,” says Mastroianni. “You need to start with very high-level models and start doing some of the analysis even before we get into implementation. You can do some very rudimentary power analysis and thermal analysis and stress analysis. Then you can perform more detailed analysis at points in the flow to see if you are still on track.”

“You have to do an inter-die physical verification, which is like an LVS flow,” says Patwardhan. “And inter-die DRC checks based on whatever rules are provided by the foundry. That has to happen at the system level. It is a tool challenge, because you have to identify unique instances belonging to each of the chiplet and verify connectivity between them. It requires more DRC checking between chiplets. Another thing is the electromagnetic interference (EMI) at the system-level. We have to model the whole system in one matrix. There is package interaction with the chiplet that impacts SI/PI. These checks have to be iterative checks and cannot be left completely until the sign-off stage.”

The creation of packaged solutions that include a silicon interposer is seen as a long-term path forward for the semiconductor industry and promises to provide scalable solutions. But the necessary tools and flows are not all there today.

The industry is taking a slower, more incremental approach to the problem which allows it to address the issues in a more piecemeal fashion. Even with passive interposers, new tasks exist in the flow and new issues must be considered earlier in the flow. Physical issues are growing as well as dealing with larger system complexity issues.

Steep Spike For Chip Complexity And Unknowns
Increased interactions and customization drive up risk of re-spins or failures.
Many Chiplet Challenges Ahead
Assembling systems from physical IP is gaining mindshare, but there are technical, business and logistical issues that need to be resolved before this will work.
Waiting For Chiplet Standards
An ecosystem is required to make chiplets a viable strategy for long-term success, and ecosystems are built around standards. Those standards are beginning to emerge today.
Chiplets For The Masses
Chiplets are technically and commercially viable, but not yet accessible to the majority of the market. How does the ecosystem get established?
What Goes Wrong In Advanced Packages
More heterogeneous designs and packaging options add challenges across the supply chain, from design to manufacturing and into the field.

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