Moore’s Law: A Status Report


Moore's Law has been synonymous with "smaller, faster, cheaper" for the past 52 years, but increasingly it is viewed as just one of a number of options—some competing, some complementary—as the chip industry begins zeroing in on specific market needs. This does not make [getkc id="74" comment="Moore's Law"] any less relevant. The number of companies racing from 16/14nm to 7nm is higher t... » read more

Biz Talk: ASICs


eSilicon CEO [getperson id="11145" comment="Jack Harding"] talks about the future of scaling, advanced packaging, the next big things—automotive, deep learning and virtual reality—and the need for security. [youtube vid=leO8gABABqk]   Related Stories Executive Insight: Jack Harding (Aug 2016) eSilicon’s CEO looks at industry consolidation, competition, China’s impact, an... » read more

Intel To Buy Mobileye


Intel today said it would acquire embedded vision leader Mobileye for roughly $15.3 billion in equity—$14.7 billion in "enterprise value"—setting the stage for a huge push by the chipmaker into the autonomous driving market. Intel has been dabbling in the automotive market for some time, starting with an unsuccessful bid to replace 8-bit microcontrollers with low-end processors. With the... » read more

Better Code With RTL Linting And CDC Verification


Automated design rule checking, or linting, has been around in RTL verification for at least a couple decades, yet still many HDL designers completely ignore this simple yet very powerful bug hunting method. Why would a busy designer need to run this annoying warning generator? The hostility against using conventional linting tools is often explained by the enormous amount of output noise, limi... » read more

Too Big To Simulate?


With system design complexity set on a steady upward trajectory, there are situations in which traditional simulation just can’t keep up. The alternative—and one being used by Google, Uber, Ford, GM, Volvo, Audi and others with autonomous vehicles— is to test cars on the road and collect data for later analysis. “They're not simulating, they're just doing it all in the real world ... » read more

On The Verge


Anyone who has been following the IoT/IoE or whatever-you-want-to-call-it movement knows we’re on the eve of far-reaching, life-altering change. There will be billions of connected devices, all streaming information to gigascale cloud datacenters using big data analytics and deep machine learning. Somewhere along the way, we’ll discover important, useful information from all this tha... » read more

Charting A New Course For Semiconductors


The semiconductor industry is at an inflection point facing challenges, including rising development costs, shrinking margins, market saturation and unprecedented consolidation. Although no stranger to boom and bust cycles, semiconductor companies are actively seeking a return to stability via a more sustainable and collaborative business paradigm. In this context, Rambus and the Global S... » read more

FPGA’s Role Expands


For more than a decade FPGA vendors argued that FPGAs would become a viable alternative to ASICs, adding programmability along with the same kind of advances in performance and power that ASICs saw at each new process node. While that never played out as they expected, FPGAs nonetheless have carved out a formidable position in the semiconductor market. Generally speaking, FPGAs today are us... » read more

High Throughput GSPS Signal Processing For FPGAs And ASICs Using Synthesizable IP Cores


This whitepaper illustrates how parallel processing synthesizable [getkc id="43" comment="IP"] cores available in Synphony Model Compiler enable Giga Samples Per Second (GSPS) throughput on FPGAs, and efficient area/power trade-offs for ASIC targets. In particular, we demonstrate how Parallel FFT, FIR, and CIC blocks enable users to scale throughput beyond achievable clock frequencies, and/or r... » read more

IP To Meet 2.5D Requirements


The semiconductor industry is still in the early stages of evolution in the realm of 2.5D, but when these devices do come out, the IP used on them will have to be brand new, according to Javier DeLaCruz, senior director of engineering at eSilicon. “The IP causes the biggest risk that you’re going to have in this implementation,” he said. “Everything else in here for making those ASIC... » read more

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