Which Chip Interconnect Protocol Is Better?


Semiconductor Engineering sat down to the discuss the pros and cons of the Compute Express Link (CXL) and the Cache Coherent Interconnect for Accelerators (CCIX) with Kurt Shuler, vice president of marketing at Arteris IP; Richard Solomon, technical marketing manager for PCI Express controller IP at Synopsys; and Jitendra Mohan, CEO of Astera Labs. What follows are excerpts of that conversation... » read more

Who Owns A Car’s Chip Architecture


Kurt Shuler, vice president of marketing at Arteris IP, examines the competitive battle brewing between OEMs and Tier 1s over who owns the architecture of the electronic systems and the underlying chip hardware. This has become a growing point of contention as both struggle for differentiation in a market where increasingly autonomous vehicles will all behave the same way. That, in turn, has si... » read more

The Murky World Of AI Benchmarks


AI startup companies have been emerging at breakneck speed for the past few years, all the while touting TOPS benchmark data. But what does it really mean and does a TOPS number apply across every application? Answer: It depends on a variety of factors. Historically, every class of design has used some kind of standard benchmark for both product development and positioning. For example, SPEC... » read more

Trust Assurance And Security Verification of Semiconductor IPs And ICs


Connected autonomous vehicles, 5G networks, Internet-of-things (IoT) devices, defense systems, and critical infrastructure use ASIC and FPGA SoCs running artificial intelligence algorithms or other complex software stacks. Vulnerable or tampered ICs can compromise the safety of people and the confidentiality, integrity, and availability of sensitive information. This paper analyzes the trust... » read more

Security From The Ground Up


Silicon and system design are complex and costly enough in the ultra-deep sub-micron era. Now factor in security. Virtually every end application requires some level of security, and, as the cybersecurity threat rises, the importance and value of trust and assurance rises as well. This is even more evident in “high-security” use cases such as smart cards used to enter buildings, SIM card... » read more

Software-Defined Hardware Gains Ground — Again


The traditional approach of running generic software on x86-based CPUs is running out of steam for many applications due to the slowdown of Moore’s Law and the concurrent exponential growth in software application complexity and scale. In this environment, the software and hardware are disparate due the dominance of the x86 architecture. “The need for and advent of the hardware accelerat... » read more

Design For Airborne Electronics


The Next Generation Air Transportation System (NextGen), an FAA-led modernization of America's air transportation system meant to make flying more efficient, predictable and safer, is currently underway as one of the most ambitious infrastructure projects in U.S. history. This is not just a minor upgrade to an aging infrastructure. The FAA and partners are in the process of implementing new ... » read more

Context-Aware Debug


Moses Satyasekaran, product manager at Mentor, a Siemens Business, examines the growing complexity of debug, which now includes software, power intent and integration, multiple clocking and reset domains, and much more, where the limitations are for debug, and how automotive, functional safety and mixed signal affect the overall process. » read more

Using FPGAs For AI


Artificial intelligence (AI) and machine learning (ML) are progressing at a rate that is outstripping Moore's Law. In fact, they now are evolving faster than silicon can be designed. The industry is looking at all possibilities to provide devices that have the necessary accuracy and performance, as well as a power budget that can be sustained. FPGAs are promising, but they also have some sig... » read more

Planning For Panel-Level Fan-out


Several companies are developing or ramping up panel-level fan-out packaging as a way to reduce the cost of advanced packaging. Wafer-level fan-out is one of several advanced packaging types where a package can incorporate dies, MEMS and passives in an IC package. This approach has been in production for years, and is produced in a round wafer format in 200mm or 300mm wafer sizes. Fan-out... » read more

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