Validating design kits requires investment and collaboration across the supply chain, but it pays off in fewer layout respins and lower risk.
The chiplet model has been proven by the early adopters. Large companies that successfully developed chips at leading nodes have integrated multiple chiplets into systems, where the entire silicon cycle is performed in-house. But the industry’s long-term goal of a free and open chiplet marketplace, in which companies of any size can reap the rewards and economies of scale associated with multi-chiplet systems, will take some time.
Two organizations, the Open Compute Project (OCP) Foundation and JEDEC, are making significant progress on this front, enabling streamlined methods of designing, assembling, testing, and validating systems-in-package (SiPs). Among the advances:
The new design kits loosely build on the concept of process design kits (PDKs), a key reason behind the semiconductor industry’s success at producing increasingly complex chips and systems. “An SoC design process has fully qualified verification methods embodied in the PDK, enabling IC designers to maximize productivity as they implement known, proven verification methods,” said Tony Mastroianni, senior director 3D-IC Solutions Engineering at Siemens EDA. “So we’re trying to extend that concept into the packaging world, but that requires a different set of design kits.”
History of PDK/assembly kits
The original concept of process design kits was developed at Texas Instruments in 1991. PDKs were created to provide design engineers with the manufacturing rules and libraries needed to use EDA tools successfully. Today, a foundry provides the technology node, constraints, models, libraries, and rule decks to a fabless firm or IDM to ensure design success.
The advent of ADKs dates back to at least 2015, when industry experts first recognized that chiplet-based packaging offered the most viable path to improving PPAC in systems. The OCP is made up of companies throughout the supply chain united in a goal of developing an open, collaborative ecosystem for building SiPs based on chiplets. This disruptive concept is altering that very supply chain.
Enter 3DK
To streamline the processes for multi-chiplet packaging, the OCP and JEDEC released assembly design kits (ADKs), test design kits (TDKs), material design kits (MDKs), package design rule manuals (DRMs), and electrical sign-off in a cross-collaborative structure called 3DK (see figure 1). [1,2,3,4]
Fig. 1: The design kits describe the chiplet’s models, the package stack-up, test pins, material properties, assembly capabilities, and electrical verification. Source: OCPSUMMIT24/Creative Commons ShareAlike 4.0 International License
Fig. 2: 3DK Design Kits, broken down into architectural planning, design and sign-off. Source: OCPSUMMIT24/Creative Commons ShareAlike 4.0 International License
The assembly design kit, also known as a package assembly design kit (PADK), introduces a signoff verification step to the process flow that was previously absent. “The intent of the PADK technology is for the layout design engineer to utilize an easy-to-use method of verifying their design,” said Ruben Fuentes, vice president of Amkor’s Design Center. “Beginning with package feature sizes and routing guidance through to the 3D interconnections and 3D package alignment, the OSAT’s PADK provides an OEM customer the peace of mind needed to ensure complete signoff verification.” [5]
Just as a semiconductor foundry bears the responsibility of conveying PDKs to their fabless customers, the outsourced semiconductor assembly and test providers (OSATs) provide assembly capabilities to system integrators and other customers. “Our vertically integrated packaging platform is built on fan-out RDL technology. This organic RDL is essentially the interposer level, which provides two advantages relative to a silicon interposer — lower insertion loss, because the organic material is a better insulator, and reduced cost,” said Lihong Cao, senior director of engineering and technical marketing at ASE.
The push for integration among materials, packaging, testing, and electrical signoff comes from the need to concurrently perform thermal, mechanical, and electrical planning at the architectural design stage. “We definitely need simultaneous collaboration to bring together innovations from the IDM design house to packaging with the OSATs and on to the system level. And we need the standardization to reuse all these IPs to leverage everyone’s efforts,” said Cao.
The OCP is calling for a unified co-design flow because advanced packages feature many interactions between layers. There is no clear separation between traditional dies and packages, like there was with monolithic chip packaging. “You can’t necessarily design a chip or a chiplet as a standalone unit,” said Siemens’ Mastroianni. “It has to work in the context of the overall system. So it’s your package design process, your interposer design process, and all your chiplets are being designed in parallel for integration in the package.”
An important step in making the kits useful involves converting key information into machine-readable formats. For example, ADKs, also known as package assembly design kits (PADKs), contain the rules that define bump pitch and size, the number of metal layers in a substrate, line size and pitch, via sizes, etc. These rules often are listed in a PDF file or Excel spreadsheet, rather than in a machine-readable format. By having just one source for these rules, each EDA vendor that supports the OCP formats can enable checks based on a shared format.
The first implementation step in 3DKs identified a standard language for describing chiplets, aimed at facilitating a plug-and-play chiplet economy. By integrating the OCP Chiplet Data Extensible Markup Language (CDXML) specification into JEDEC JEP30: Part Model Guidelines, chiplet builders can electronically provide a standardized chiplet part description to their customers, paving the way for automating system-in-package (SiP) design and manufacturing using chiplets. The CDX spells out the models that chiplet suppliers should deliver. These are the rules that define the pitch, the spacing, the type of connections between the chiplets and interposer, interposer and substrate, chiplet-to-chiplet interface, etc.
Companies wishing to list their chiplets on the marketplace should include all chiplet models in a machine-readable format. Other documentation, such as an IC datasheet for each ASIC, should describe the device, pinout, operating conditions, and electrical/mechanical specifications. Where applicable, the chiplet vendor should document the package assembly vendor/process that the chiplet is compatible with.
Different OCP working groups are specifying and updating the design rules for each sector, as each has different needs.
Materials matter
Because materials selection in advanced packaging significantly influences the mechanical, thermal, and electrical behavior of 3D stacks, the key properties of materials must be readily accessible to designers, substrate providers, foundries, and OSATs. Historically, the design leads responsible for these workflows worked directly with the material vendors using information that typically was defined in PDF documents and entered directly into their workflow scripts in an ad hoc manner.
Instead, a materials design kit (MDK) consolidates these material properties in a set of centralized design kits delivered in a reusable, machine-readable format that EDA workflows can consume. The material properties are instrumental in performing PCB and package-level Signal Integrity (SI) analysis and Power Integrity (PI) analysis, as well as mechanical design workflows.
Critical properties include the dielectric constant and loss tangent of low-k materials, thermal coefficients of expansion, thermal conductivity, Young’s modulus (elasticity), line-edge roughness, etc. These properties are provided not just for bulk materials but also at greatly reduced dimensions where the interface properties dominate overall behavior.
“The design leads for the 3D-IC analysis, reliability analysis, and mechanical design/signoff analysis tasks will work with the chiplet, interposer, and AFB substrate vendors, and the package assembly vendors to define the material property requirements and capture the salient material properties required for the respective workflows,” states the MDK.
Testability
The chiplet Test Design Kit (TDK) within OCP provides a comprehensive framework to support testability in the planning, design, and manufacturing of chiplet-based systems.
The TDK includes precise definitions of such terms as “pad,” “sacrificial pad,” and various pad processes (e.g., solder balls, copper pillars, and hybrid bond pads). Sacrificial pads are used exclusively during testing and are then excluded from the final product. The test flow includes detailed guidelines for incorporating test requirements at every stage of the development.
To streamline communication between design, test, and assembly, the standard format, CDXML, defines pad locations, structures, and test parameters. All of the design kits support emerging technologies, their definitions, and workflows such as backside power delivery or optical interconnects.
Assembly and packaging
By standardizing file formats, design rules, and tolerances, the ADK enables efficient data exchange and interoperability across platforms, promoting innovation and reducing development cycles. The kit also supports the integration of advanced design techniques like AI and machine learning into the assembly process, ensuring scalability.
Advanced packaging has a variety of stakeholders, including systems integrators, OSATs, substrate providers, foundries, and fabless companies. Interest in ADKs/PADKs is heightened due to the need to optimize the device’s intended package performance with complete connectivity verification, design rule checking, and assembly validation. “This is possible by beginning with clear and proven manufacturing and assembly checks that can be implemented during the initial layout phase, thereby reducing the need for rework of the design layout during post-process checking,” said Amkor’s Fuentes.
Reference designs
The OCP has already begun the process of proving the utility of the various design kits. High-density fan-out packaging is the perfect candidate for testing these approaches because the HDFO layout file size can be up to 1.5Gb, with more than 1 million defined items in the database. The single-threaded processor capability and the maximum CPU speed measured in megahertz will significantly affect design editing and verification processing time.
“Experiencing the benefits that an HDFO package assembly design kit can provide requires allocating time and money, but to what extent will greatly depend on the hardware and software currently available to the HDFO designer,” Fuentes said. “However, building from an existing design workflow will help with a quick implementation process. Four key areas make for a successful PADK implementation — high-end computer hardware, compatible software, advanced training, and a qualified support team.” [5]
One segment of the electronics market that is keen to adopt ADKs is the U.S. military. HRL Laboratories, the U.S. Air Force, and Cadence recently demonstrated an RDL-first, chip-last fan-out co-design process with fine-pitch chip interconnects, thermal heat spreader, and electrical shielding with >95% connectivity. Leveraging an advanced silicon interposer with minimum line/space features and pad pitch, the heat spreader functions as both a shield between chips and a heat dissipator. A commercial CMOS foundry provided the RDL first process and bumping, while HRL provided an additional redistribution layer, thermocompression bonding of gold bumps, die attach, and metal forming processes. [6]
In this work the PDK streamed in the layout (GDS). Then, macros placed the pads, bumps, and metal shield in the layout. Once all the pins were defined, a macro generated the symbol view of the chip. The symbol view is placed in a schematic design where symbol terminals are connected to pins or terminals of another chip. Next, the schematic generates the layout, and the router placements are verified. The design rule check highlights any violations. Once the violations are fixed, engineers extract the RC parasitics based on closed-form equations.
Conclusion
The semiconductor industry is at a critical juncture in its evolution. Higher levels of cooperation are needed to take the next step from proprietary chiplet-based systems to standard formats, flows, and design rules. This will allow a greater number of companies to participate in the chiplet ecosystem.
Guidelines, flows, design kits, and standards available through the OCP and JEDEC aim to streamline the design to assembly, test, and packaging process all the way to the system integrator level. Advanced packaging, which currently accounts for a small fraction of systems produced, is poised for rapid growth once the industry agrees on how these manufacturing flows should occur.
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