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Knowledge Center

Functional Design and Verification

Functional Design and Verification is currently associated with all design and verification functions performed before RTL synthesis.


The development of an integrated circuit involves many phases, each requiring a different set of skills. The general methodology attempts to segregate the flow so as to enable some degree of specialization. While there are functions performed across the boundaries of these segregated areas, a general attempt is made to minimize the extend of these.
The principle methodology is use (2014) is centered around a Register Transfer Level (RTL) description. Design is considered to be the creation of this RTL description which feeds a logic synthesis flow. Logic Synthesis forms the bridge into the implementation flow, which deals with issues such as the physical placement of the devices onto a substrate and the resulting implications of that placement.

An new flow is emerging called Electronic system Level (ESL) which starts at a higher level of abstraction and, using high-level synthesis (HLS) transforms this down to an RTL description.

Functional verification is the process of ensuring that the RTL description conforms to a specification.

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