中文 English

Best Practices For Deploying Cliosoft SOS On AWS


Semiconductor Integrated Circuits (ICs) are at the center of a number of modern technological innovations. To keep up with the ever-increasing pace of innovation, IC design teams require robust, scalable design management (DM) solutions to enable seamless global collaboration and increase productivity. This eBook outlines the advantages of, and best practices, for deploying Cliosoft SOS design ... » read more

Rocky Road To Designing Chips In The Cloud


EDA is moving to the cloud in fits and starts as tool vendors sort out complex financial models and tradeoffs while recognizing a potentially big new opportunity to provide unlimited processing capacity using a pay-as-you-go approach. By all accounts, a tremendous amount of tire-kicking is happening now as EDA vendors and users delve into the how and why of moving to the cloud for chip desig... » read more

Virtuoso ADE Assembler


Cadence Virtuoso ADE Assembler is an advanced design and simulation environment that extends the capabilities of Virtuoso ADE Explorer, adding all the tests needed to fully verify a design over all operational, process, and environmental conditions. As more analysis is required, users can take incremental advantage of the Virtuoso Variation Option to do more advanced statistical analysis on the... » read more

Using Cliosoft SOS Design Management Platform In The Cloud


In this eBook, we will talk about the various scenarios for how designers can leverage Cliosoft’s SoC design management platform in the cloud (Amazon Web Services and Google Cloud Platform) to successfully tapeout their SoCs. Click here to access the eBook. » read more

When Is Verification Done?


Even with the billions of dollars spent on R&D for EDA tools, and tens of billions more on verification labor, only 30% to 50% of ASIC designs are first time right, according to Wilson Research Group and Siemens EDA. Even then, these designs still have bugs. They’re just not catastrophic enough to cause a re-spin. This means more efficient verification is needed. Until then, verificati... » read more

5G NR Design For eMBB


This white paper examines the design challenges for eMBB products and provides examples of how these challenges can be overcome using the co-design capabilities in Cadence AWR Design Environment software. Click here to download with registration. » read more

The Evolution Of Digital Twins


Digital twins are starting to make inroads earlier in the chip design flow, allowing design teams to develop more effective models. But they also are adding new challenges in maintaining those models throughout a chip's lifecycle. Until a couple of years ago, few people in the semiconductor industry had even heard the term "digital twin." Then, suddenly, it was everywhere, causing confusion ... » read more

Designer And IP Tracks Swell With Focus On ML, Security And Traditional EDA Methodologies


What are designers keenly interested in as the 57th Design Automation Conference (DAC) approaches? If you said machine learning (ML), you’d be only partially right. Based on designer and IP tracks submissions to the 57th edition of the venerable electronics-industry event, ML – how to design with it and optimize EDA tools and flows using it – is a hot topic. But so too are more traditi... » read more

An Eye For An AI


AI comes in multiple forms and flavors. The challenge is choosing the right one for the right purpose, and recognizing that just because AI can be applied to a particular process or problem doesn't mean it should be. While AI has been billed as a ideal solution for just about every problem, there are three primary requirements for a successful application. First, there needs to be sufficient q... » read more

RTL Architect: Simply Better RTL


Electronic devices play a key role in society. They connect us to one another through voice, video and chat. They entertain, educate, protect and heal us in new and ever-expanding ways. They have changed the way we work, live and play. Silicon chips are the fast beating heart (2 to 3 billion beats per second) of these devices. For decades, the relentless advancements in semiconductor process te... » read more

← Older posts