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Knowledge Center

serializer/deserializer (SerDes)

A transmission system that sends signals over a high-speed connection from a transceiver on one chip to a receiver on another. The transceiver converts parallel data into serial stream of data that is re-translated into parallel on the receiving end.


A serializer/deserializer (serdes or SerDes)* circuit converts parallel data—in other words, multiple streams of data—into a serial (one bit) stream of data that is transmitted over a high-speed connection, such as LVDS, to a receiver that converts the serial stream back to the original, parallel data. A clock system puts parallel into a serial by taking bits from the multiple streams and alternating them on a up and down parts of the signals.

Both the serializer and deserializer are functional blocks on the transmitting and receiving chips. The two functional blocks are Parallel In Serial Out (PISO) and the Serial In Parallel Out (SIPO).

LVDS (low-voltage differential signaling) has two wires for one bit of data.

Types of SerDes: PCI Express, SATA, XAUI

SerDes has emerged as the primary solution in chips where there is a need for fast data movement and limited I/O, but this technology is becoming significantly more challenging to work with as speeds continue to rise to offset the massive increase in data.

A serializer/deserializer consists of functional blocks in a chip that are used to convert parallel data into serial data, allowing designers to speed up data communication without having to increase the number of pins. But as the volume of data increases, and as more devices are connected to the Internet and ultimately the cloud, the need to move more data much faster is growing. This, in turn, has made SerDes design increasingly complicated.

Much of the demand for high-speed SerDes comes from large data centers, where the current state-of-the-art throughput is 100 Gbps. Standards from IEEE and the Optical Internetworking Forum are defining higher and higher data rates on a single lane, which allow data to be aggregated to much larger systems. Then, to move SerDes technology to the next level of performance, one of the major advancements is the adoption of PAM4 signaling above 28Gbps.

Fig. 1: Typical high-speed I/O architecture. Source: Mentor, a Siemens Business

“SerDes is the perfect storm of analog precision and analog circuitry,” said Mick Tegethoff, director of product management at Mentor, a Siemens Business in a Jan. 2019 story. “We have worked with customers over different technology generations, and the challenges have become tougher.”


Source: Texas Instruments’ video “SerDes Basics.”

*pronounced “sir deeze” or “sir dess”)


High-Speed SerDes At 7nm