Systems & Design

Efficient Verification Of Mixed-Signal Series IP Using UVM

Universal Verification Methodology tackles mixed-signal verification with this robust technique.


Interface IP are an integral part of systems-on-chips (SoC) that include mobile, automotive, or networking applications and are primarily used for transmitting data over a physical medium between a host and device. The mixed-signal nature of the IP makes verification a challenging task, requiring special considerations for digital and analog sections. This paper describes a robust mixed-signal verification technique using the Universal Verification Methodology (UVM) to verify SerDes designs. We also explain the modifications to standard UVM to add mixed-signal verification concepts to the methodology. With the help of new verification components that can be reused across multiple protocols with ease, mixed signal designs can be verified just as easily. This paper also describes the implemented mixed-signal verification methodology using the USB Type-C design

Authors: Varun R, Senior Design Engineer, Cadence, and Vinayak Hegde, Design Engineering Manager, Cadence

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