High-Performance SerDes Enable The 5G Wireless Edge

The importance of a high-speed, low-latency cellular network for AI-powered IoT devices.


Investment at the core of the global internet is red hot. The number of hyperscale data centers jumped to 700 worldwide at the end of 2021, and with more than 300 in the pipeline, should rise to over 1000 by 20241. In the span of five years, total hyperscale data centers will have doubled. And as the raw number shoots up, more powerful compute and networking hardware is rapidly being deployed, so both the total square footage and the computing power-per-square-foot are headed skyward. And the upshot is: it’s still not enough.

The growth in data traffic and the demand for real-time (latency-sensitive) applications is relentless. To keep pace, analysts are predicting investment at the network edge will outstrip that of the core in the years ahead. To reduce latency, AI/ML inferencing will increasingly be deployed at the edge of the network and in smart IoT end-point devices. As vast numbers of these AI-powered IoT devices will be mobile, portable, or off the wireline network, the importance of a high-speed, low-latency cellular network is key.

That’s where 5G wireless comes into the picture. Relative to its 4G predecessor, 5G offers up to 10X the throughput (data rate), 100X higher capacity, and 10X greater device density all at 1/10th the latency. With peak data rates going from 1 Gbps to 20 Gbps and latency going from 10 ms to 1 ms, 5G makes it possible to offer a host of real-time applications and services. To achieve this performance, 5G requires significant investments and changes in infrastructure compared to previous generations. These changes for 5G, as for any other infrastructure that relies on high-speed transfer of data, processing, and re-distribution of processed data, rely heavily on ultra-high speed and low-latency SerDes for data communication.

Legacy 4G network front-haul infrastructure is comprised of two main elements: the remote radio head (RRH) at the top of the cell tower and the baseband unit (BBU) at the bottom. The RRH is connected to the BBU using fiber optics and communicate via the common public radio interface (CPRI) protocol. CPRI was introduced during the 3G generation to increase speed beyond that of traditional co-axial cabling used previously.

In the 5G generation, the above infrastructure continues to exist, but 5G also brings the deployment of cloud or centralized radio access network (C-RAN) based architecture. C-RAN is a centralized, cloud-computing based architecture for radio access networks that not only supports 5G but provides backwards compatibility with earlier 4G/3G generations. The C-RAN infrastructure enables higher density, more throughput, and increased bandwidth.

The RRH in front-haul network designs contain an RF transceiver, data converter circuitry, and digital signal processors. Implementation of the RRH involves conversion of an analog signal into digital and vice versa, and the serial data communication interface between data converter units are governed by the JEDEC standard JESD204.

In 5G networks, this style of tower architecture continues to exist, but the internal workings require much higher speed capabilities than 4G implementations. To support 5G data rates, upgrades to the existing communications interfaces of both CPRI and JESD were required. CPRI increased from 12.1 Gbps to 24.33 Gbps and the JESD204 standard increases speed from 12.5 Gbps with JESD204B to 32.5 Gbps with JESD204C.

In a CPRI front-haul architecture, data streams are nominally formed by I and Q (in-phase and quadrature) streams. Jitter in the SerDes clocking or variation in the signal latency introduces errors in the I and Q data streams. A high-speed SerDes designed for CPRI applications requires very low transmit clock jitter, very low recovered clock jitter, low latency, and ultra-low latency variation. Special consideration and techniques are required to reduce the latency variation in the SerDes to create an ideal interface for these long-reach networking applications.

With JESD204C, in addition to maintaining low jitter and latency values, one of the key challenges of digital converter interfaces is that upstream and downstream data rates can be asymmetric. In many SerDes architecture implementations, supporting RX and TX asymmetric data rates results in significant overhead in power and area consumption. An advanced clocking mechanism in addition to a careful optimization of power and area is required to reduce the overhead of asymmetric operation. These considerations, combined with a significant increase in channel loss when moving from lower data rates to higher data rates, require a SerDes with advanced equalization and adaptation scheme to cover such a broad specification.

Rambus offers 32G SerDes tailored to meet the needs of 5G CPRI and JESD204C. These SerDes are architected to provide the ultra-low jitter, ultra-low latency and efficient asymmetric operation needed for 5G. With over 30 years of leadership in high-performance interfaces, and industry renown as the expert in signal and power integrity, all backed by world-class engineering support, we can help you accelerate to market your 5G chip designs.

1 Synergy Research Group, March 2022

Additional resource:
Website: Rambus 32G Multi-protocol SerDes PHY

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