Redefining XPU Memory For AI Data Centers Through Custom HBM4: Part 2

By Archana Cheruliyil - 09 Dec, 2024 - Comments: 0

This is the second in a three-part series from Alphawave Semi on HBM4 and gives insights into HBM implementation challenges. Click here for part 1, for an overview on HBM, and in part 3, we will introduce details of a custom HBM implementation. Implementing a 2.5D System-in-Package (SiP) with High Bandwidth Memory (HBM) is a complex process that spans across architecture definition, designi... » read more

Redefining XPU Memory For AI Data Centers Through Custom HBM4: Part 1

By Archana Cheruliyil - 26 Nov, 2024 - Comments: 1

This is the first of a three-part series on HBM4 and gives an overview of the HBM standard. Part 2 will provide insights on HBM implementation challenges, and part 3 will introduce the concept of a custom HBM implementation. Relentless growth in data consumption Recent advances in deep learning have had a transformative effect on artificial intelligence (AI) and the ever-increasing volume of ... » read more

One Chip Vs. Many Chiplets

By Ed Sperling - 20 Nov, 2024 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the growing list of challenges at advanced nodes and in advanced packages, with Jamie Schaeffer, vice president of product management at GlobalFoundries; Dechao Guo, director of advanced logic technology R&D at IBM; Dave Thompson, vice president at Intel; Mustafa Badaroglu, principal engineer at Qualcomm; and Thomas Ponnusw... » read more

Extending Chip Lifetime With Safer Voltage Scaling

By Eyal Fayneh - 12 Nov, 2024 - Comments: 0

What if your chips lived 20% longer without compromising performance, and even while reducing power consumption? How would it affect your product’s reliability and cost? What would be the effect on your profitability? With the demand for longer-lasting chips growing across industries, designers and reliability engineers face increasing pressure to ensure their products perform correctly fo... » read more

Outsmarting Silent Data Corruption In AI Processors With Two-Stage Detection

By proteanTecs - 12 Nov, 2024 - Comments: 0

Silent data corruption is on the rise following advancements in semiconductor technology. The explosion in AI for speech, image, video, and text processing leads to a growing complexity and diversity of hardware systems, bringing an increased risk to data integrity. SDC rate is much higher than software engineers expect, undermining the hardware reliability they used to take for granted. Rec... » read more

Is Liquid Cooling Right For Your Data Center?

By Mark Seymour - 17 Oct, 2024 - Comments: 0

We live in an exciting time—liquid cooling, which once seemed more trouble than it’s worth, is fast becoming an accepted and sought-after technology in the data center industry. That said, it’s still a complex technology to implement, especially in legacy facilities. Is your data center ready to operationalize liquid cooling? Liquid cooling in the data center Liquid cooling in the d... » read more

Data Center Digital Twin Return On Investment From An Environmental Standpoint

By Cadence - 16 Oct, 2024 - Comments: 0

Data center operators face growing pressure to enhance sustainability. Understanding where inefficiencies occur is the first step toward making impactful changes. Cadence Reality DC Digital Twin helps you identify inefficiencies, implement solutions, and track improvements. This white paper reveals how Cadence Reality DC Digital Twin can save an average of 316MWh annually, delivering a retur... » read more

From Reaction To Prevention In Data Center RAS

By Noam Brousard - 15 Oct, 2024 - Comments: 0

The rise of artificial intelligence (AI), cloud services, and IoT has fueled the rapid expansion of hyperscale data centers. These massive facilities house thousands of servers, all working to support an increasingly digital world. But as the scale of data centers grows, so too does the need for reliable and high-performance semiconductors. Semiconductor failures and inconsistencies can cause s... » read more

Redefining RAS in Datacenters with Real-Time Health Monitoring

By proteanTecs - 15 Oct, 2024 - Comments: 0

Abstract Hyperscale datacenters require intense computational power for compute-intensive tasks, such as AI, data analytics, machine learning, and big data processing. They leverage parallel processing across multiple computers, in high-density servers, to handle complex tasks efficiently. This uses specialized, powerful processors and training and inference of specific GPUs or ASICs. Such c... » read more

The Cost Of EDA Data Storage And Processing Efficiency

By Adam Kovac - 09 Oct, 2024 - Comments: 0

Engineering teams are turning to the cloud to process and store increasing amounts of EDA data, but while the compute resources in hyperscale data centers are virtually unlimited, the move can add costs, slow access to data, and raise new concerns about sustainability. For complex chip designs, the elasticity of the cloud is a huge bonus. With advanced-node chips and packaging, the amount of... » read more

← Older posts

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.