Next-Generation Ethernet Interconnects For 400G Hyperscale Data Centers


The need for higher bandwidth with efficient connectivity increases as hyperscale data centers transition to faster, flatter, and more scalable network architectures, such as the 2-tier leaf-spine, as seen in Figure 1. The leaf-spine architecture requires massive interconnects as each leaf switch fans-out to every spine switch, maximizing connectivity between servers. Hardware accelerators, art... » read more

Power Issues Grow For Cloud Chips


Performance levels in traditional or hyperscale data centers are being limited by power and heat caused by an increasing number of processors, memory, disk and operating systems within servers. The problem is so complex and intertwined, though, that solving it requires a series of steps that hopefully add up to a significant reduction across a system. But at 7nm and below, predicting exactly... » read more

Enabling Device Intelligence


The explosive growth in silicon and software for artificial intelligence applications is transforming everything we know about connectivity, energy-efficiency, mobility, and security. Machine learning (ML) techniques are already used in computer vision, object recognition, speech recognition, and big data analytics. Deep learning (DL) algorithms and neural networks are pushing both silicon and ... » read more

Huge Performance Gains Ahead


Rambus Chief Scientist Craig Hampel talks about what will drive the next big performance gains after Moore’s Law, from the data center to the edge. https://youtu.be/ItHCsei7YTc » read more

Week in Review: IoT, Security, Auto


Cybersecurity Jens (Atom) Steube, a cybersecurity researcher and creator of the Hashcat password cracking tool, was probing for vulnerabilities in the new WPA3 security standard for Wi-Fi routers. WPA3 presents a robust defense against hacking, yet Steube discovered a security flaw in routers using WPA/WPA2 – one that leaves Wi-Fi passwords enabled with Pairwise Master Key Identifiers vulner... » read more

High-Speed SerDes At 7nm


eSilicon’s David Axelrad discusses the challenges with 56Gbps and 112Gps SerDes, and why the switch from analog to digital is required for performance and low power. https://youtu.be/E-CU8TLvjjc » read more

On-Chip Monitoring Of FinFETs


Stephen Crosher, CEO of Moortec, sat down with Semiconductor Engineering to discuss on-chip monitoring and its impact on power, security and reliability, including predictive maintenance. What follows are excerpts of that conversation. SE: What new problems are you seeing in design? Crosher: There are challenges emerging for companies working on advanced nodes, including scaling and trans... » read more

Data Center Power Poised To Rise


The big power-saving effort that kept U.S. data-center power consumption low for the past decade may not keep the lid on much longer. Faced with the possibility that data centers would consume a disastrously large percentage of the world's power supply, data center owners, and players in the computer, semiconductor, power and cooling industries ramped up effort to improve the efficiency of e... » read more

7nm Design Challenges


Ty Garibay, CTO at ArterisIP, talks about the challenges of moving to 7nm, who’s likely to head there, how long it will take to develop chips at that node, and why it will be so expensive. This also raises questions about whether chips will begin to disaggregate at 7nm and 5nm. https://youtu.be/ZqCAbH678GE » read more

Ensuring Chip Reliability From The Inside


Monitoring activity and traffic is emerging as an essential ingredient in complex, heterogeneous chips used in automotive, industrial, and data center applications. This is particularly true in safety-critical applications such as automotive, where much depends on the system operating exactly right at all times. To make autonomous and assisted driving possible, a mechanism to ensure systems ... » read more

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