Multiphysics Simulations for AI Silicon to System Success


Achieving power efficiency, power integrity, signal integrity, thermal integrity and reliability is paramount for enabling product success by overcoming the challenges of size and complexity in AI hardware and optimizing the same for rapidly evolving AI software. ANSYS’ comprehensive chip, package and system solutions empower AI hardware designers by breaking down design margins and siloed de... » read more

Chiplets, Faster Interconnects, More Efficiency


Big chipmakers are turning to architectural improvements such as chiplets, faster throughput both on-chip and off-chip, and concentrating more work per operation or cycle, in order to ramp up processing speeds and efficiency. Taken as a whole, this represents a significant shift in direction for the major chip companies. All of them are wrestling with massive increases in processing demands ... » read more

Bottlenecks For Edge Processors


New processor architectures are being developed that can provide two to three orders of magnitude improvement in performance. The question now is whether the performance in systems will be anything close to the processor benchmarks. Most of these processors doing one thing very well. They handle specific data types and can accelerate the multiply-accumulate functions for algorithms by distri... » read more

Power/Performance Bits: April 16


Faster CNN training Researchers at North Carolina State University developed a technique that reduces training time for deep learning networks by more than 60% without sacrificing accuracy. Convolutional neural networks (CNN) divide images into blocks, which are then run through a series of computational filters. In training, this needs to be repeated for the thousands to millions of images... » read more

Week in Review: IoT, Security, Auto


Internet of Things Smart-building technology is a factor in marketing new facilities to prospective tenants. The new Cambridge Crossing development in Cambridge, Mass., aspires to attract tech-oriented tenants much like nearby Kendall Square, this analysis notes. Philips has agreed to lease seven floors in Cambridge Crossing’s first office building, making that location its North American he... » read more

Why 56Gb/s And 112Gb/s SerDes Matter In Our Daily Social-Media-Driven Lives


Hyper-scalers and service providers are moving from 100GbE to 400GbE Ethernet rates and beyond. Wireline and wireless networks are driving new architectures to support the move from 4G LTE to 5G infrastructure. These transitions are driven by the increasing global IP traffic as the world becomes more connected and digital. At the same time, the decentralization of the cloud and data centers are... » read more

AI Chips: NoC Interconnect IP Solves Three Design Challenges


New network-on-chip (NoC) interconnect IP is now available for artificial intelligence (AI) systems-on-chip (SoC). Arteris IP launched the fourth generation of the FlexNoC interconnect IP with a new optional AI package. The novel NoC interconnect technologies solves many data flow problems in today’s AI designs. Innovative features address the requirements of the next-generation of AI chips t... » read more

Making IP Friendlier


Semiconductor Engineering sat down to discuss IP tracking and management with Ranjit Adhikary, vice president of marketing for ClioSoft; Jim Bruister, director digital systems (since retired) at Silvaco; Marc Greenberg, product marketing group director at Cadence; and Kelvin Low, vice president of marketing at Arm. What follows are excerpts from that conversation. Part one can be found here. ... » read more

Next-Generation Ethernet Interconnects For 400G Hyperscale Data Centers


The need for higher bandwidth with efficient connectivity increases as hyperscale data centers transition to faster, flatter, and more scalable network architectures, such as the 2-tier leaf-spine, as seen in Figure 1. The leaf-spine architecture requires massive interconnects as each leaf switch fans-out to every spine switch, maximizing connectivity between servers. Hardware accelerators, art... » read more

Power Issues Grow For Cloud Chips


Performance levels in traditional or hyperscale data centers are being limited by power and heat caused by an increasing number of processors, memory, disk and operating systems within servers. The problem is so complex and intertwined, though, that solving it requires a series of steps that hopefully add up to a significant reduction across a system. But at 7nm and below, predicting exactly... » read more

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