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Cache Coherent Interconnect for Accelerators (CCIX)

Interconnect standard which provides cache coherency for accelerators and memory expansion peripheral devices connecting to processors.


Cache Coherent Interconnect for Accelerators, or CCIX, is an industry standard specification to enable coherent interconnect technologies between general-purpose processors and acceleration devices for efficient heterogeneous computing.

Using the technology available before the release of CCIX, the general flow of data between a CPU and accelerator would have been very batch-oriented. The CPU would transfer data, possibly using a direct memory access (DMA), from main memory into the accelerator. The accelerator would crunch on the data until it had completed and would send an interrupt back to the CPU indicating its completion. At that point, the resulting data would be transferred back into main memory. This whole process has long latency, and this promotes a very granular operation.

Rather than creating a new standard from scratch, CCIX is built on top of PCI Express. The PCIe physical and data link layers can be used unmodified. CCIX adds a modified transaction layer and a new link and protocol layer.

CCIX creates a system from connected components, with all of them having native access to the same memory. If you were to have designed accelerators that were on a single piece of silicon, all of the accelerators would have had access to all of the resources of the SoC. CCIX is attempting to enable the same functionality at the system level.

By bringing the notion of cache coherence between the CPU and accelerator, CCIX bypasses much of the overhead. Data structures can be created in memory, and a pointer to it sent to the accelerator. The accelerator can crunch on the data immediately, possibly making local copies of data only when it actually needs it. It is also possible that the data is being continuously updated.

The standard is created and managed by the CCIX Consortium. The effort was started by Xilinx in 2016, when it needed an efficient architecture to connect its devices, which were being used as accelerators within a datacenter. The consortium was formed in March 2017, along with Arm and some EDA and IP partners.

The specification is limited to member companies, but an evaluation version is available to the public. The latest specification can be found on the CCIX website.


Hybrid Memory