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DRAM: Dynamic Random Access Memory

Single transistor memory that requires refresh


Dynamic Random Access Memory (DRAM) stores data in a capacitor. These capacitors leak charge so the information would fades unless the charge is refreshed periodically. Because of this refresh requirement, it is a dynamic memory as opposed to SRAM and other static memory.

The advantage of DRAM is its structural simplicity: only one transistor and a capacitor are required per bit, compared to six transistors in SRAM. This allows DRAM to reach very high density.

Several new types of DRAM are being developed that utilize characteristics of Silicon on Insulator (SOI). Instead of using a capacitor to store the value, the floating body effect inherent in the manufacturing process is used. Several commercial variants such as the Twin Transistor RAM (TTRAM) being developed by Renesas and the Z-RAM Zero capacitor RAM in development by Innovative Silicon.

Ferroelectric RAM (FeRAM or FRAM) is a random access memory similar in construction to DRAM but uses a ferroelectric layer instead of a dielectric layer to achieve non-volatility.

In today’s systems, the memory/storage hierarchy is straightforward. SRAM is integrated into the processor for cache. DRAM is used for main memory. Disk drives and solid-state storage drives are used for storage.

DRAM is based on a one-transistor, one-capacitor (1T1C) cell structure. The cells are arranged in a rectangular, grid-like array. In simple terms, a voltage is applied to the transistor in the DRAM cell. The voltage is then given a data value. It is then placed on a bit-line. This, in turn, charges the storage capacitor. Each bit of data is then stored in the capacitor.

Over time, the charge in the capacitor will leak or discharge when the transistor is turned off. So, the stored data in the capacitor must be refreshed every 64 milliseconds.

The industry has managed to scale the DRAM for decades. But soon, the DRAM will run out of steam, as it is becoming more difficult to scale the 1T1C cell. Beyond 20nm, the DRAM is expected to scale two or three iterations in the 1xnm regime, which is referred to as 1xnm, 1ynm and 1znm.

The DRAM was invented by Dr. Robert Dennard at the IBM Thomas J. Watson Research Center in 1966.


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