Knowledge Center
Knowledge Center

Power-Aware Design

Techniques that analyze and optimize power in a design


Energy consumption is a major, if not the major, concern today. The world is facing phenomenal growth of demand for energy from the Far East coupled with the unabated and substantial appetite for energy in the U.S. and Europe. At the same time, population growth, economic expansion and urban development will create greater demand for more personal-mobility items, appliances, devices and services.

Recognizing these worrisome trends, the U.S. Department of Energy (DOE) has identified the reduction of energy consumption in commercial and residential buildings as a strategic goal. The Energy Information Administration at DOE attributed 33% of the primary energy consumption in the U.S. to building space heating and cooling-an amount equivalent to 2.1 billion barrels of oil. At these levels, even a modest aggregate increase in heating ventilation and air conditioning (HVAC) efficiency of 1% will provide direct economic benefits to people, enabling reduction and better management of electric utility grid demand, and reducing dependence on fossil fuels. In addition to the global relevance of efficient energy usage, there are the micro-economic and convenience concerns of families, where energy consumption is putting pressure on domestic budgets and where battery life of home mobile appliances is becoming a major selection factor for consumers.

What can electronics makers do to help? Energy usage can be optimized at the chip, board, box, system, and network level. At each of these levels there are major gains that can be achieved. Low-power design has been a substantial research theme for years in IC design. Several important results have been used to limit energy consumption by fast components such as microprocessors and digital signal processors. However, while the trend has been improving, the energy consumption of, for example, Intel and AMD microprocessors is still very important, so that additional research is warranted. As we traverse layers of abstractions towards systems and networks, the attention paid to low energy consumption is not increasing proportionally; an important issue to consider moving forward on the energy conservation path.

Companies should take a holistic view in the energy debate. By carefully managing the interactions between the different layers of abstraction and by performing a global tradeoff analysis, companies may take a leadership position. We understand that at this time, enough attention has not been paid to energy consumption as the design goals have been centered on performance and cost. We also believe that no one company or institution acting alone can tackle all the issues involved. Leveraging the supply chain, EDA companies, partners’ research organizations and universities offers a way to corral the available resources and focus on the problem.

Focusing on the IC design area, process engineers cannot solve the problem alone: 90nm and smaller process nodes are burning more power with increased design complexity and clock frequencies. Static power is becoming the predominant source of energy waste. It is up to the design, EDA and IP community to create methodologies that support better designs, higher performance, lower costs, and higher engineering productivity-in the context of low-power.

Dr. Alberto Sangiovanni-Vincentelli – Foreword to “A Practical Guide to Low-Power Design” authored and used with permission from Cadence Design Systems.