Knowledge Center
Navigation
Knowledge Center

Metastability

Unstable state within a latch
popularity

Description

When the input signal to a data latch changes within the setup-and-hold window around the transition of the latching clock, the latch output can become metastable at an intermediate voltage between logical zero and one. Consider a simplified latch implementation as shown below.

A simplified latch

The metastable state is a very high-energy state. Because of noise in the chip environment, this metastable voltage gets disturbed and eventually resolves to a logical value. The resolution time is dependent upon the load on the latch output and the gain through the feedback loop. It is impossible, however, to predict this logical value.


The metastability energy curve

There is an inherent delay in the resolution of the metastable output as shown in the timing diagram. This logical and timing uncertainty introduces unreliable behavior in the design and, without proper protection, can cause it to fail in unpredictable ways.


Metastability timing diagram

For synchronous clock designs, timing closure with static timing analysis ensures that all paths meet timing specifications; metastability is avoided and the designs operate reliably.

Original page contents provided by Real Intent