Avoiding Pitfalls While Specifying Timing Exceptions

Timing exceptions can be powerful tools in the right hands, but a mistake in specifying them can result in chip failure.


Timing exceptions are commonly used to meet timing goals while implementing a design. These exceptions typically cover asynchronous paths like clock domain crossings (CDC) or synchronous paths where timing is either not relevant (e.g., set_false_path command in SDC) or can be relaxed (e.g., set_multicycle_path command in SDC), instructing static timing analysis (STA) and implementation tools to provide additional leeway to meet timing requirements along these paths.

Implementation tools such as synthesis and place and route make use of this information to better optimize the implementation and achieve better area, timing, power or routability. While timing exceptions are potent tool in the hands of implementation engineers, any mistake in specifying them can result in a chip failure. In this white paper we will discuss various types of exceptions and describe how to avoid pitfalls using a systematic verification approach. Some experimental results are presented at the end.

To download this white paper, click here.