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Eliminate Silicon Respins With Netlist CDC Verification


Clock domain crossing (CDC) verification has been an integral part of modern chip design flow for quite sometime. Traditionally CDC verification has been done during the RTL stage. However, for advanced designs and complex flows, there is significant logic optimization during RTL synthesis as well as backend flows at the netlist stage. This mandates clock domain crossing verification a must for... » read more

Constraint-Based Verification Of Clock Domain Crossings


There are many measures of the ever-growing size and complexity of semiconductor devices: die area, transistor count, gate count, size of memories, amount of parallel processing and more. All these factors mean more time spent in design, but they also have a major impact on verification. Since virtually all industry studies show verification time and effort growing faster than design, this impa... » read more

Avoiding Pitfalls While Specifying Timing Exceptions


Timing exceptions are commonly used to meet timing goals while implementing a design. These exceptions typically cover asynchronous paths like clock domain crossings (CDC) or synchronous paths where timing is either not relevant (e.g., set_false_path command in SDC) or can be relaxed (e.g., set_multicycle_path command in SDC), instructing static timing analysis (STA) and implementation tools to... » read more