Systems & Design

Constraint-Based Verification Of Clock Domain Crossings

Pre-silicon verification for all clock domain crossings (CDC) is critical. Learn about CDC verification challenges and techniques.


There are many measures of the ever-growing size and complexity of semiconductor devices: die area, transistor count, gate count, size of memories, amount of parallel processing and more. All these factors mean more time spent in design, but they also have a major impact on verification. Since virtually all industry studies show verification time and effort growing faster than design, this impact must be considered when planning chip projects.

The clock domain crossing (CDC) design and verification process is no exception to these trends. The number of independent clock domains in chips is growing steadily, and careful design techniques are required to avoid data corruption and other serious problems. Many of these design flaws, if allowed to escape to silicon, can result in a chip that does not work and may require a long and costly re-fabrication to fix. Thus, pre-silicon verification for all CDCs is critical. Traditional verification methods such as simulation and static timing analysis are inefficient and unable to provide complete verification. Only a combination of static, simulation and formal techniques can exhaustively verify CDCs and prove that there are no related bugs in a design. This white paper provides background on clock domains and their verification challenges, and then presents a solution for thorough CDC verification.

Click here to download the white paper.

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