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The Weather Report: 2018 Study On IC/ASIC Verification Trends

Increased design size is only one dimension of the growing complexity challenge.

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Nobel Laureate Bob Dylan observed, “You don’t need a weatherman to know which way the wind blows.” Similarly, we can get a feeling for where our industry is going by attending to the flow of thought at conferences, on line, or in our daily business. But that gives us only a small window to observe the hurricane-like forces of the very large and complicated, extremely dynamic global semiconductor industry. So we humbly present ourselves as a weatherman of sorts with our bi-annual survey of important trends in functional verification.

This article is the third of a four part series presenting the findings of the 2018 Wilson Research Group Functional Verification Study. In the previous two articles (Trends in FPGA Effectiveness and Trends in FPGA Verification and Adoption), we focused on FPGA design and verification trends. Now we will shift to IC/ASIC trends. In this article we will look at design and design resources that reflect growing design complexity as well as trends in verification technology adoption.

IC/ASIC Design Trends
Figure 1 shows trends from the 2014, 2016, and 2018 studies in terms of active IC/ASIC design projects by design sizes (gates of logic and datapath, excluding memories). Keep in mind that the graph represents the percentage of study participants, not silicon volume.

One interesting observation from the 2018 study is the continuing increase in design participants working on designs of less than 100K gates. This is due to a number of participants working on smaller sensor chips for IoT and automotive devices. Thus, we see that the number of participants working on designs smaller than 500K gates has increased from 18 percent in 2014 to 29 percent in 2018. As we’ll see, this yielded some interesting study results as these very small projects typically do not apply advanced verification techniques, which can bias overall verification technique adoption trends.


Figure 1. IC/ASIC Design Sizes

The rise in small designs notwithstanding, the electronic industry continues to move to larger designs. In fact, 33 percent of today’s design projects are over 40M gates, while 31 percent are between 1M and 40M gates.

But increased design size is only one dimension of the growing complexity challenge. One industry driver that has had a substantial impact on IC/ASIC design and verification complexity is the emergence of new layers of design requirements (beyond basic functionality), which did not exist years ago; for example, clocking requirements, security requirements, safety requirements, and requirements associated with hardware-software interactions.


Figure 2: New Requirements Continue to Drive Increasing Complexity

What has changed significantly in designs since the original Collett studies is the dramatic movement to SoCs. In 2004, Collett found that 52 percent of designs contained one or more embedded processors.

Our 2018 study found that 66 percent of designs had embedded processors, as shown in Figure 3. You might note that in 2016 we found that 73 percent of projects involved designs with embedded processors. So why the decrease? Well, again, we saw a significant increase in smaller designs. In this case, this large increase of smaller designs had an overall impact on the number of projects working on designs containing embedded processors. If we ignore these smaller designs and only look at designs greater than 1M gates, we did not see a statistically significant change in the number embedded processors from 2016 to 2018.


Figure 3. Number of Embedded Processors in an IC/ASIC Design

Another interesting trend is the increase in the number of multiple embedded processors in a single SoC. For example, 48 percent of design projects today are working on designs that contain two or more embedded processors, while 13 percent of today’s designs include eight or more embedded processors. SoC class designs add a new layer of verification complexity to the verification process that did not exist with traditional non-SoC class designs due to hardware and software interactions, new coherency architectures, and the emergence of complex network on-a-chip interconnects.

In addition to the increasing number of embedded processors contained within an SoC, it is not uncommon to find in the order of a hundred or more integrated IP blocks within today’s more advanced SoCs. Many of these IP blocks have their own clocking requirements, which often present new verification challenges due to metastability issues involving signals that cross between multiple asynchronous clock domains.

In Figure 4, we see that 89 percent of all IC/ASIC designs today have two or more asynchronous clock domains.


Figure 4. Number of Asynchronous Clock Domains in IC/ASIC Designs

One of the challenges with verifying clock domain crossing issues is that there is a class of metastability bugs that cannot be demonstrated in simulation on an RTL model. To simulate these issues requires a gate-level model with timing, which is often not available until later stages in the design flow. However, static clock-domain crossing (CDC) verification tools have emerged to automatically identify clock domain issues directly on an RTL model at earlier stages in the design flow.

Many projects are implementing security features in their designs, as shown in Figure 5. Examples of security features include security assurance hardware modules (e.g., a security controller) that are designed to safely hold sensitive data, such as encryption keys, digital right management (DRM) keys, passwords, and biometrics reference data. These security features add requirements and complexity to the verification process.


Figure 5. IC/ASIC design projects implementing security features

Another example of increasing requirements contributing to complexity relates to safety-critical designs. In Figure 6, we see an increase in the number of IC/ASIC projects working under one of multiple safety-critical development process standards or guidelines.


Figure 6. IC/ASIC safety-critical design projects

For those projects working under a safety-critical development process standard or guideline, in Figure 7 we show the specific breakdown for the various standards. Note that some projects are required to work under multiple safety standards or guidelines; for example, IEC61508 and IEC61511.


Figure 7. Safety-critical development standard used on IC/ASIC project

IC/ASIC designs are clearly growing in complexity, which impacts verification effort and effectiveness. Now we will discuss the growing IC/ASIC design project resource trends due to this rising design complexity.

IC/ASIC Resource Trends
Figure 8 shows the percentage of total IC/ASIC project time spent in verification. As you would expect, the results are all over the spectrum; whereas, some projects spend less time in verification, other projects spend more. The average total project time spent in verification in 2018 was 53 percent, which did not change significantly between 2012 through 2018. This is remarkable considering that designs have grown in terms of size and complexity; yet the overall percentage of project time spent on verification has remained relatively constant.


Figure 8. Percentage of IC/ASIC Project Time Spent in Verification

Perhaps one of the biggest challenges in design and verification today is identifying solutions to increase productivity and control engineering headcount. To illustrate the need for productivity improvement, all we need to do is look at trends in increasing engineering headcount. Figure 9 shows the mean peak number of engineers working on projects between 2007 and 2018. Again, this is an industry average since some projects have many engineers while other projects have few — with differing ratios. You can see that the mean peak number of verification engineers today is just slightly greater than the mean peak number of design engineers. In other words, there are, on average, more verification engineers working on a project than design engineers. This situation has changed significantly since 2007.


Figure 9. Mean Number of Peak Engineers per IC/ASIC Project

Another way to comprehend the impact of today’s project headcount trends is to calculate the compounded annual growth rate (CAGR) for both design and verification engineers working on projects. Between 2007 and 2014, the industry experienced a 3.8 percent CAGR for design engineers and an impressive 12.6 percent CAGR for verification engineers. Clearly, the double-digit increase in verification engineers during this period was a major project cost management concern and is one indicator that the industry under-scoped the verification effort during this period. To address growing verification complexity the industry was forced to mature its verification processes. Today, we find that the demand for verification engineers has flattened between 2014 and 2018. Essentially we have reached a one-to-one ratio in terms of mean peak number of design and verification engineers.

But verification engineers are not the only project stakeholders involved in the verification process. Design engineers spend a significant amount of their time in verification too, as shown in Figure 10. In 2014, design engineers spent on average 47 percent of their time involved in design activities and 53 percent of their time in verification. While in 2018 we found that design engineers spent on average 54 percent of their time involved in design activities and 46 percent of their time in verification. One factor contributing to the increased percentage of time a design engineer spends in design activities is the growing number of design requirements we discussed earlier.


Figure 10. Where IC/ASIC Design Engineers Spend Their Time

Figure 11 shows where verification engineers spend their time (on average). Our study found that verification engineers spend more of their time in debugging than any other activity. In fact, we found that the time spent debugging grew significantly between 2016 (39%) and 2018 (44%).


Figure 11. Where IC/ASIC Verification Engineers Spend Their Time

IC/ASIC Verification Technology Adoption Trends
As we’ve observed, the adoption of SoC-class designs in the mid-2000 timeframe created challenges for the IC/ASIC market in addressing increased verification complexity. This maturing of IC/ASIC projects’ processes is clearly visible when comparing various simulation-based verification technology adoption trends from 2007, 2012, and 2018, as shown in Figure 12.


Figure 12. IC/ASIC Verification Technology Adoption Trends (2007-2018)

Today we find that, in general, most IC/ASIC projects have matured and adopted a common set of simulation-based verification techniques as part of their IP and subsystem verification process. As the IC/ASIC industry matures, as expected, we’ve seen a trend of verification technology adoption peaking (that is, leveling off), as shown in Figure 13.


Figure 13. IC/ASIC Dynamic Verification Adoption Trends

Recall that for the past few studies we have seen a trend in terms of an increasing number of IC/ASIC designs of less than 500K gates. We remarked that these small projects often do not adopt advanced verification techniques, which can bias the overall industry verification technique adoption trends and can result in what appears as a slight decline in adoption in some cases. The reality is that there has been little change in terms of adoption as the market matures.

Figure 14 shows the IC/ASIC adoption trends for formal property checking (e.g., model checking), as well as automatic formal applications. Examples of automatic formal application tools include: SoC integration connectivity checking, deadlock detection, X semantic safety checks, coverage reachability analysis, and many other properties that can be automatically extracted and then formally proven. Note, not included in the automatic formal application trend data are clock-domain crossing CDC tools.


Figure 14. IC/ASIC Formal Technology Adoption

We see in Figure 14 that formal property checking has grown at a 5.4 percent CAGR since 2012, while automatic formal applications has grown at a 9.2% CAGR. Again, keep in mind the previous discussion on the increasing number of small projects, which are often less mature in their verification processes. As a result this can bias the adoption trends.

According to Pedestal Research, the emulation market value was forecast to be $376M in 2018 and expected to grow at a 7.6 percent CAGR over the next few years. Pedestal Research also claims that the FPGA prototyping market value was forecast to be $66M in 2018 (not including home grown solutions) and expected to grow at a 9.9 percent CAGR.

Historically, the simulation market has depended on processor frequency scaling as one means of continual improvement in simulation performance. However, as processor frequency scaling levels off, simulation-based techniques are unable to keep up with today’s growing complexity. This is particularly true when simulating large designs that include both software and embedded processor core models. Hence, acceleration techniques are now required to extend SoC verification performance for very large designs. In fact, emulation and FPGA prototyping have become key platforms for SoC integration verification where both hardware and software are integrated into a system for the first time. In addition to SoC verification, emulation and FPGA prototyping are used today as platforms for software development.

Figure 15 describes various reasons why projects are using emulation, while Figure 16 describes why FPGA prototyping was performed. You might note that the results do not sum to 100 percent since multiple answers were accepted from each study participant.


Figure 15. Why Emulation Was Performed


Figure 16. Why FPGA Prototyping Was Performed

Hopefully this report will help you to know which way the wind blows as you make what could be critical decisions about where to invest your money, time, and energy on verification technology and tools.

In the final installment of this series, we will discuss IC/ASIC trends in language and library adoption, power management, and verification results, and we will conclude with a deeper dive into two somewhat surprising phenomena revealed in the data: the relationship between verification maturity and non-trivial bug escapes into production and the effect of safety critical design practices on the level of silicon success.

Want to go deeper into formal and clock domain crossing solutions to current challenges? Check out these whitepapers: Improving Quality and Time-to-Market with Formal Verification and Five Steps to Quality CDC Verification.



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