tag: metastability

Screening For Silent Data Errors
By Anne Meixner - 10 Jan, 2023 - Comments: 0

Engineers are beginning to understand the causes of silent data errors (SDEs) and the data center failures they cause, both of which can be reduced by increasing test coverage and boosting inspection on critical layers. Silent data errors are so named because if engineers don’t look for them, then they don’t know they exist. Unlike other kinds of faulty behaviors, these errors also can c... » read more

Formal Verification Ensures The Perseverance Rover Lands Safely On Mars
By Joseph Hupcey III - 28 Apr, 2022 - Comments: 0

By Joe Hupcey III and Kevin Campbell Safely landing a spacecraft anywhere on Mars is a complex, high-risk challenge. Even worse, the most scientifically interesting areas of the planet are guarded by boulders, ditches, and tall cliffs — land formations that aren’t very welcoming to vehicles. Such was the case with the Mars Perseverance Rover's Landing Site: Jezero Crater. It’s not an e... » read more

Early Detection Of Reset Domain Crossing Errors
By Joe Mallett - 13 May, 2021 - Comments: 0

Many aspects of system-on-chip (SoC) designs are growing, including the numbers of gates, memories, clock domains, reset domains, power domains, on-chip buses, and external interfaces. A recent blog post focused on reset domain crossings (RDCs) and the requirements for effective pre-silicon verification of these trouble-prone structures. If properly applied, a solution meeting these requirement... » read more

Effective Clock Domain Crossing Verification
By Rahul Chirania - 15 Oct, 2020 - Comments: 0

As chips grow ever larger and more complex, gate count and amount of embedded memory grow dramatically. The number of clock domains is also increasing steadily. Several dozen different clocks are common in today’s chips, with some designs having more than a thousand domains. There are several reasons for this explosion: Multiple external interfaces with distinct clock requirements Lic... » read more

Dynamic CDC Jitter For Clock Domain Crossing (CDC) Signoff
By Himanshu Bhatt - 16 Jan, 2020 - Comments: 0

By Himanshu Bhatt and Paras Mal Jain Detecting and debugging deep sequential CDC convergences using structural CDC verification is extremely difficult since doing a flat analysis on large designs has capacity related challenges, and even if verification tools can complete the analysis, it becomes a nightmare to debug the violations with complex sequential logic. Thus arises the need for dyna... » read more

Three Steps To Complete Reset Behavior Verification
By Chris Kwok - 14 Nov, 2019 - Comments: 0

By Chris Kwok, Priya Viswanathan, and Ping Yeung Reset architectures are notoriously complex and difficult to verify. Today’s SoCs contain highly complex reset distributions and synchronization circuitry. Often, reset trees can be larger than clock trees and have many of the same potential issues. Verifying that a design can be correctly reset under all modes of operation presents signi... » read more

FPGA And System Designs Get To Market Faster Leveraging ASIC-Proven Analysis Tools
By Chris Giles - 30 May, 2019 - Comments: 0

Increasing power constraints have resulted in finer-grained partitioning of designs into functional domains that can have clocks disabled or, more drastically, are powered down entirely. Systems are required to adaptively manage clocks to minimize switching power. Performance and area constraints have led to the abandonment of more conservative practices in favor of more aggressive designs; ... » read more

The Weather Report: 2018 Study On IC/ASIC Verification Trends
By Harry Foster - 11 Apr, 2019 - Comments: 0

Nobel Laureate Bob Dylan observed, “You don’t need a weatherman to know which way the wind blows.” Similarly, we can get a feeling for where our industry is going by attending to the flow of thought at conferences, on line, or in our daily business. But that gives us only a small window to observe the hurricane-like forces of the very large and complicated, extremely dynamic global semico... » read more

The Problem With CDCs
By Louie De Luna - 24 Nov, 2015 - Comments: 0

Part of the Planning Process in DO-254 is knowing the appropriate FPGA tools and capabilities that you need and intend to use for your FPGA design. Particularly if your FPGA device operates with multiple asynchronous clocks which necessitates using advanced verification techniques targeting anomalies related to clock domain crossings (CDCs). Typical electronic design automation (EDA) tools f... » read more

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