FPGA And System Designs Get To Market Faster Leveraging ASIC-Proven Analysis Tools


Increasing power constraints have resulted in finer-grained partitioning of designs into functional domains that can have clocks disabled or, more drastically, are powered down entirely. Systems are required to adaptively manage clocks to minimize switching power. Performance and area constraints have led to the abandonment of more conservative practices in favor of more aggressive designs; ... » read more

The Weather Report: 2018 Study On IC/ASIC Verification Trends


Nobel Laureate Bob Dylan observed, “You don’t need a weatherman to know which way the wind blows.” Similarly, we can get a feeling for where our industry is going by attending to the flow of thought at conferences, on line, or in our daily business. But that gives us only a small window to observe the hurricane-like forces of the very large and complicated, extremely dynamic global semico... » read more

The Problem With CDCs


Part of the Planning Process in DO-254 is knowing the appropriate FPGA tools and capabilities that you need and intend to use for your FPGA design. Particularly if your FPGA device operates with multiple asynchronous clocks which necessitates using advanced verification techniques targeting anomalies related to clock domain crossings (CDCs). Typical electronic design automation (EDA) tools f... » read more