Author's Latest Posts

Early Detection Of Reset Domain Crossing Errors

Many aspects of system-on-chip (SoC) designs are growing, including the numbers of gates, memories, clock domains, reset domains, power domains, on-chip buses, and external interfaces. A recent blog post focused on reset domain crossings (RDCs) and the requirements for effective pre-silicon verification of these trouble-prone structures. If properly applied, a solution meeting these requirement... » read more

Requirements For Exhaustive SoC Reset Domain Crossing Checks

It is common to read that the numbers of clock domains and power domains in system-on-chip (SoC) designs are increasing, but for some reason there is less discussion about resets. There is no doubt that the number of reset domains is also rising; studies have shown that the single reset of twenty years ago has been replaced by a complex network of 40-50 domains in many chips and even 150 in som... » read more

Automation And Fault Simulation Of Safety-Critical FPGA Designs

Functional safety is a major challenge for field programmable gate arrays (FPGAs) and other semiconductor designs. Safety requirements go beyond traditional verification, which focuses on design bugs. Chips in safety-critical applications must be able to handle a variety of faults from sources such as temperature and power extremes, device aging, radiation, ionization and component failures. Ap... » read more

Verification Of Multi-Cycle Paths And False Paths

All chip designers know that they must take special care to avoid metastability problems when they have multiple, asynchronous clock domains. In contrast, a design in which all clocks are synchronous may appear simple. Logic synthesis ensures that the shortest paths between registers don’t have races and that the longest paths fit within the target cycle time. However, single-clock design is ... » read more