Don’t Have A Meltdown Over A Spectre In Your SoC


You may be concerned about last year’s widely published Spectre and Meltdown vulnerabilities affecting most processors. Are your phone and computer OK? Or more importantly, if you are designing or verifying a System on Chip (SoC), do you have a specter in your design? Let’s first look at what these two vulnerabilities are and how they may be affecting your system. Both vulnerabilitie... » read more

Formal Verification Of RISC-V Cores


By Sven Beyer RISC-V is hot and stands at the beginning of what may be a major shift in the industry. Even a cursory review of upcoming conferences programs and recent technical articles makes that clear. While it is still early in the evolution of the processor architecture, there is certainly the potential that RISC-V will be a game-changer in the IP and semiconductor industry. As “a fre... » read more

The Problem With Post-Silicon Debug


Semiconductor engineers traditionally have focused on trying to create 'perfect' GDSII at tape-out, but factors such as hardware-software interactions, increasingly heterogeneous designs, and the introduction of AI are forcing companies to rethink that approach. In the past, chipmakers typically banked on longer product cycles and multiple iterations of silicon to identify problems. This no ... » read more

Can Debug Be Tamed?


Debug consumes more time than any other aspect of the chip design and verification process, and it adds uncertainty and risk to semiconductor development because there are always lingering questions about whether enough bugs were caught in the allotted amount of time. Recent figures suggest that the problem is getting worse, too, as complexity and demand for reliability continue to rise. The... » read more

Pushing AI Into The Mainstream


Artificial intelligence is emerging as the driving force behind many advancements in technology, even though the industry has merely scratched the surface of what may be possible. But how deeply AI penetrates different market segments and technologies, and how quickly it pushes into the mainstream, depend on a variety of issues that still must be resolved. In addition to a plethora of techni... » read more

Connectivity Checking Is A Perfect Fit For Formal Verification


Formal verification has traditionally been regarded as an advanced technique for experts to thoroughly verify individual blocks of logic, or perhaps small clusters of blocks. However, if you talk to anyone involved in the field these days, you’ll find that the majority of formal users are running applications (“apps”) targeted for specific verification problems. Further, many of these app... » read more

EDA Grabs Bigger Slice Of Chip Market


EDA revenues have been a fairly constant percentage of semiconductor revenues, but that may change in 2019. With new customers creating demand, and some traditional customers shifting focus from advanced nodes, the various branches of the EDA tool industry may be where sticky technical problems are solved. IC manufacturing, packaging and development tools all are finding new ways to handle t... » read more

Taming Concurrency


Concurrency adds complexity for which the industry lacks appropriate tools, and the problem has grown to the point where errors can creep into designs with no easy or consistent way to detect them. In the past, when chips were essentially a single pipeline, this wasn't a problem. In fact, the early pioneers of EDA created a suitable language to describe and contain the necessary concurrency ... » read more

The Fibonacci Calculator


The holiday season is all about traditions, and the annual holiday puzzle has become a tradition here at OneSpin. Two years ago, we challenged engineers everywhere to solve the famous Einstein’s Riddle using a formal tool. We received some interesting solutions. Last year, we drew an even bigger response to our invitation to tackle the “World’s Hardest Sudoku.” These puzzles are fun, of... » read more

Week In Review: Design, Low Power


Tools & IP UltraSoC debuted functional safety-focused Lockstep Monitor, a set of configurable IP blocks that are protocol aware and can be used to cross-check outputs, bus transactions, code execution, and register states between two or more redundant systems. It supports all common lockstep / redundancy architectures, including full dual-redundant lockstep, split/lock, master/checker, and... » read more

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