Gaps In Verification Metrics


As design complexity has exploded, the verification effort has likewise grown exponentially, with many different types of verification being applied to different classes of design. A recent panel discussion with leading chipmakers examined this topic in an effort to shed light on design health and quality, measuring the success of verification, knowing when verification is complete, being on... » read more

Bugs That Kill


Are simulation-resistant superbugs stifling innovation? That is a question Craig Shirley, president and CEO of Oski Technology, asked a collection of semiconductor executives over dinner. Semiconductor Engineering was invited to hear that discussion and to present the key points of the discussion. To promote free conversation, the participants, who are listed below, asked not to be quoted di... » read more

Functional Safety: Art Or Science?


Nowadays, most hardware development projects deploy functional verification flows that include UVM-based constrained-random testbenches and formal verification. High design complexity, tough budget constraints, and short time to market are the norm, not the exception. Advanced verification is a necessity for many engineering teams. In our increasingly connected world, where billions of IoT devi... » read more

Verification As A Flow


Semiconductor Engineering sat down to discuss the transformation of verification from a tool to a flow with Vladislav Palfy, global manager application engineering for OneSpin Solutions; Dave Kelf, chief marketing officer for Breker Verification Systems; Mark Olen, product marketing group manager for Mentor, A Siemens Business; Larry Melling, product management director, System & Verificati... » read more

The Skies Over EDA Are Finally Cloudy


EDA companies have been talking for years about providing access to their tools in the cloud, including more articles than I can count with titles about the EDA forecast being cloudy, clouds on the horizon, and so forth. The title of this post continues the dubious tradition of cloud-based puns, but there’s no future tense involved. Recent announcements from several EDA companies make it appe... » read more

Blog Review: June 27


Applied Materials' Sundeep Bajikar argues that to realize the full potential of AI, new computing architectures are necessary, otherwise AI will quickly become unaffordable. Synopsys' Iain Singleton considers why it may not always be necessary to start at the reset state during formal verification and how to use abstractions to get a head start on bug hunting. Cadence's Meera Collier look... » read more

Welcome Verification 3.0


Leave it to Jim Hogan, managing partner of Vista Ventures, to look further out at the changing horizon of verification than the rest of us and to make sense of it in what he calls Verification 3.0. In his executive summary, he outlined the significant advancements in functional verification over the past 20 years, such as hybrid verification platforms in Verification 1.0 and hardware/software c... » read more

A Combined Design And Verification Flow For Safety-Critical Designs


By Tom Anderson and Srikanth Rengarajan I welcome my co-author for today’s post, Srikanth Rengarajan, vice president of product and business development from Austemper Design Systems. We would like to focus on safety-critical designs, a topic very much in the news these days because of the public’s fascination with autonomous vehicles. This consumer category now joins medical electron... » read more

How To Build Functional Safety Into Your Design From The Start


The focus on functional safety IP is rapidly growing and we’re seeing this growth not just in automotive but in many other markets including, avionics, medical, industrial and railways, where systems need to efficiently identify and mitigate the occurrences of faults, and where more confidence is required with respect to the design practises employed for the development of IP. Currently, m... » read more

Why Your FPGA Synthesis Flow Requires Verification


When you think about it, logic synthesis is a vital but rather intimidating part of modern chip design. This process takes a high-level description of intended functionality, written in an RTL language that looks more like software than hardware, and implements it using the low-level building-block library of an ASIC or FPGA device. The resulting gate-level netlist must meet a variety of requir... » read more

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