Author's Latest Posts

Using Symbolic Simulation For SRAM Redundancy Repair Verification

Innovations in Very Deep Sub-Micron technologies, such as the advent of three-dimensional FinFET transistor structures, have facilitated the implementation of very large embedded SRAM memories in System-on-Chip (SoC) designs to the point where they occupy the majority of the chip die area. To get maximum memory capacity on the smallest die area, SRAM bitcells are designed with the minimum possi... » read more

Cell Library Verification Using Symbolic Simulation

Standard cell libraries have been a mainstay of chip design for many decades since the inception of logic synthesis and composition methodologies. Cell library IP typically contains Verilog models describing the cell functionality, schematic derived transistor level netlists, place and route views, physical layout views, post-layout extracted netlists as well as characterized timing and power m... » read more

Detecting Electrical Hazards Incurred By Inter-Voltage Domain Crossing In Custom SRAMs

Fast-growing markets, such as 5G, biotechnology, AI, and automotive, are driving a new wave of low-power semiconductor design requirements and, hence, more aggressive low-power management techniques are needed. Consequently, even large macros within a chip, such as SRAMs, now feature multiple voltage domains to limit power draw during light-sleep, deep-sleep, and shutdown-low-power modes. These... » read more