What Happened To Statistical Static Timing Analysis?

SSTA was supposed to be a critical element in the design flow. Things didn’t work out as planned.


About five years ago if you listened to the marketing messages in the EDA industry, you would have thought it would be impossible to produce chips without statistical static timing analysis (SSTA).

Fast forward to now and the industry seems to have put this approach on the back burner. So what happened?

“The idea was that if you modeled your design instead of using a corner-based approach where you said, ‘This is the worst corner and I will just tying my design to this,’ there was this thought process that said, ‘If I think about this as a statistical problem I could say maybe rather than going to the absolute worst case I could go to the 99% or 98% worst-case and get an improved improvement in poor performance or power and pay a little price in yield.’ That was sort of the motivation for the whole effort,” according to Rob Aitken, an ARM Fellow.

While the technology had a lot of promise, it didn’t get off the ground for two reasons. First, the statistics turned out to be a lot more complicated than initially thought. “The idea of being able to easily predict this is where the 99% line or 98% line will be at a fab is actually a very difficult problem. The second thing that was a big deal for IP providers like ARM was that the characterization cost for producing the statistical models was astronomical, so it was at least 10x the cost of characterizing a normal standards cell library for example,” he said.

Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys, agreed. “We had one customer at one time that said it was going to take so many CPU hours to do the characterization that it was going to take approximately 100 man years.”

Characterization requires statistical SPICE models that have to come from the foundry, so the designers must have a willing foundry partner that wants to provide that data, explained Ruben Molina, director of product marketing for timing sign-off at Cadence.

“You’ve got to have a characterization tool that can create the statistical libraries,” Molina said. “Once you have all that stuff then you can actually run something. There are already barriers before you can even do anything with the statistical tool. But once you have those things then the whole concept of mean values for timing plus some standard deviations are sort of a foreign concept to static timing analysis engineers. They are used to absolute numbers, and when you tell them that the number is mean plus a three sigma value basically that means that you’re looking at a number that represents a 99.8% probability that other 0.2% kind of makes them uneasy. Those are the things that make people hesitate about doing this.”

Another issue that slowed things down was that there was a lot of hubbub at 65nm and 40nm when it was believed that the on-chip variation (OCV) margins, or timing derates, that engineering teams are using today were going to blow up and wouldn’t be able to meet the performance metrics. Fortunately, design engineers found ways to reduce their OCV values.

Aitken said the basic motivations still exist, though. “People still want the idea of being able to push their process a little bit and not have to fit in these corners and so they went to a variety of ways of approximating.”

Out of that motivation arose ExtremeDA, acquired by Synopsys a year ago, that developed a technology approach called parametric on-chip variation (POCV), a much more lightweight version of SSTA that tried to provide some benefits closer to full statistical without all of the drawbacks.

Hoogenstryd said there is currently only one customer in the world that’s actually using POCV to do tapeouts and signoff on their design, but there is interest from other customers. “In fact, we made the investment of actually integrating the POCV methodology that the ExtremeDA developed and patented, and we’ve put that into our PrimeTime set of timing tools. We have that technology in the hand of a few limited customers.”

POCV is seen to have some benefits over another technology that replaced statistical called advanced OCV (AOCV), a table-based methodology that was used to mimic statistical. But Hoogenstryd added, “You didn’t have to do all the characterization stuff and you didn’t have to take the run-time hit in the static timing tools and so forth, and that was something that was actually developed before statistical…in partnership with a few Japanese semiconductor companies and one in Europe. That one sort of fell into the chasm as well. And then, lo and behold, we found it becoming a very popular technique in the Japanese semiconductor companies. We’ve since enhanced it and made it faster. That took about three or four years to get broader adoption. AOCV is the technique that’s being used by the leading-edge customers, as well as that next wave of customers.”

AOCV is used to model the variation and the statistical nature of it. “We see that as the technique that’s going to continue to be used at 28nm and the customers that are putting their toes in the water in terms of exploring 20nm are also going to be using this,” Hoogenstryd noted.

Synopsys expects POCV will be used beginning at 16nm and 14nm. “The reason for that is not necessarily that those technologies need it, because AOCV doesn’t solve the problems or that the other technologies couldn’t benefit from POCV. It’s really more of an ecosystem thing because in order to take advantage of this technique, you’d have to have the library models, you have to do the characterization, you have to change your characterization methodology somewhat, you have to validate it.”

Given that 28nm is pretty mature from a library and IP perspective, the foundries and IP providers don’t want to go back and re-characterize everything to support a new capability unless it has a huge ROI. As such, POCV will probably be appropriate for 16 or 14nm finFETs because there’s too much of the ecosystem momentum at 20 and 28nm, Hoogenstryd said.

Ultimately, designers don’t care about achieving statistical timing analysis—they need to have timing signoff across all corners.

“Essentially, the competing thought or the competing technology was more efficient multi-corner flows because you can’t just go to your VP of engineering and say, ‘Statistically, I’m meeting timing signoff and 60% of the chips will meet our spec and the other 30% we know aren’t going to work,’” observed Carey Robertson, product marketing director at Mentor Graphics. “What is more powerful is to go to that VP of engineering and say, ‘For every interconnect corner that TSMC is telling me they can produce, we have met timing closure.’ That may mean a little bit more guard-banding than a statistical approach, but we will meet timing closure. Then the discussion is how can we meet timing closure in less time or in the same time as previous nodes that essentially meant parallelism rather than doing one corner at a time serially. There was an evolution of tools to do five corners at the same time or seven corners, and in those cases where the tools can support it we would just throw it at additional hardware.”

Moving forward there is a discussion creeping back in. What about sensitivity analysis? What about statistical modeling? What about double patterning that incurs more corners. If it goes from 5 to 10, is that double the computer time? There are huge challenges once again.

“What I see customers asking for is rather than give me more corners or more parallelism or statistical,” Robertson said. “What we need to be able to do is understand where the variations have an impact and focus our analysis there. By that I mean at a net level or at a cell level. Don’t give customers 10 or 15 more corners to simulate across but understand, for double patterning for instance, if the masks are going to shift. If they shift a couple nanometers in any one direction, how many of those nets will be impacted as it applies to timing closure? It’s probably in the single-digit percentages. At the end of the day we don’t want statistics, we want deterministic. We want to know our chips are going to work and we want to fix real problems.”

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