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Knowledge Center

High-Level Synthesis (HLS)

Synthesis technology that transforms an untimed behavioral description into RTL


High-level synthesis (HLS) is a technology that assists with the transformation of a behavioral description of hardware into an RTL model. It is considered to be part of an electronic system level (ESL) design flow.

The input description is an untimed description of functionality written in C, C++ or SystemC. HLS tools also exist that use Matlab, Bluespec or OpenCL as their input language. The tools assist with the selection of an architecture that will optimize the performance, area and power of the implementation.

The untimed functionality may be augmented with a description of the interface that the block is to use for connectivity into the rest of the design. This interface may define communications protocols that can in turn affect the synthesis process.

HLS tools extract the available parallelism in the input description, schedule the operations, allocate the necessary resources and optimize the sharing of those resources so as to minimize the area while maintaining the necessary performance.

While HLS is applicable to all types of design, the tools provide the most benefit to algorithmic blocks, such as video decoders, wireless compression schemes and encryption/decryption applications. These algorithms generally have loops, involve memory accesses and are amenable to pipelining.

Commercial tools vary in several ways, including the input languages that they accept, the amount of automation they provide, quality of results and integration with other aspects of an ESL flow.

Standardization efforts are underway within Accellera to define a synthesis subset of C/C++/SystemC so that users are kept away from using constructs that may only work in one implementation.

High-Level Synthesis Blue Book

High-Level Synthesis: from Algorithm to Digital Circuit

BSV by Example


Speeding Up Verification Using SystemC