Distributed Design Implementation


PV Srinivas, group director for R&D at Synopsys, talks about the impact of larger chips and increasing complexity on design productivity, why divide-and-conquer doesn’t work so well anymore, and how to reduce the number of blocks that need to be considered to achieve faster timing closure and quicker time to market. » read more

Static Verification Of Low Power Designs


Are there any chips designed today that don’t have limitations on their power consumption? For smartphones and tablets, increasing the time between charges is a clear product differentiator and a frequent design goal. Power consumption is also an issue for Internet-of-Things (IoT) devices, many of which are in inaccessible locations where battery replacement or recharge is difficult. Even com... » read more

Portable Stimulus And Digital Twins


It has been a year since Accellera's Portable Test and Stimulus Specification became a standard. Semiconductor Engineering sat down to discuss the impact it has had, and the future direction of it, with Dave Kelf, chief marketing officer for Breker Verification Systems; Larry Melling, product management director for Cadence; Tom Fitzpatrick, strategic verification architect for Mentor, a Siemen... » read more

The Case For Embedded FPGAs Strengthens And Widens


The embedded FPGA, an IP core integrated into an ASIC or SoC, is winning converts. System architects are starting to see the benefits of eFPGAs, which offer the flexibility of programmable logic without the cost of FPGAs. Programmable logic is especially appealing for accelerating machine learning applications that need frequent updates. An eFPGA can provide some architects the cover they ne... » read more

Fusion Compiler Unified Physical Synthesis


This white paper discusses how Fusion Compiler's unified physical synthesis optimization technologies addresses the time-to-market pressure and delivers the quality of results required for advanced process node leading-edge designs. Also learn about how unified physical synthesis seamlessly shares technologies and common engines between synthesis and place-and-route domains to deliver the best ... » read more

Week In Review: Design, Low Power


M&A SMIT Holdings acquired S2C, a provider of FPGA prototyping hardware and software as well as interfaces and accessories, for $19 million, plus up to US$2 million in milestone based payments to the key management team. S2C was founded in 2003. SMIT, based in Hong Kong, makes pay TV broadcasting access and mobile point-of-sale payment systems for the Chinese market. Tools & IP Syn... » read more

Is Synthesis Still Process-Independent?


For many years, the idea that the release of a new process node from one of the major silicon foundries would require you to update your synthesis flow was a non-starter. Synthesis used the available timing, area and power models in the libraries and that was the beginning and end of the discussion. With the arrival of physical synthesis, physical effects could be taken into consideration in... » read more

Changing The Design Flow


Synopsys’ Michael Jackson talks with Semiconductor Engineering about why it’s becoming necessary to fuse together various pieces of digital design. https://youtu.be/AOWh4wjw-ps » read more

Implementation Of An Asynchronous Bundled-Data Router For A GALS NoC In The Context Of A VSoC


Designs of asynchronous networks-on-chip are of growing interest because a complete asynchronous implemen- tation can solve the synchronization problems of large networks. However, asynchronous circuits suffer from the lack of proper design flows because their functionality often relies on timing constraints, which are not extensively supported by common CAD synthesis tools. This paper proposes... » read more

Why Your FPGA Synthesis Flow Requires Verification


When you think about it, logic synthesis is a vital but rather intimidating part of modern chip design. This process takes a high-level description of intended functionality, written in an RTL language that looks more like software than hardware, and implements it using the low-level building-block library of an ASIC or FPGA device. The resulting gate-level netlist must meet a variety of requir... » read more

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