Timing Closure At 7/5nm

Why shifting left in a complex design is critical.


Mansour Amirfathi, director of application engineering at Synopsys, examines how to determine if assumptions about design are correct, how many cycles are needed for a particular operation and why this is so complicated, and what happens if signals get out of phase.


Kevin Nugent says:

There are other techniques that can be used to close timing eg pipelining, register retiming, useful skew etc apart from multi cycle path constraints and false paths.

Could also be due to poor RTL coding that we had long combinatorial paths and recoding could be necessary here to resolve this issue. So writing optimised efficient RTL code is important here too.

So if pipelining is added during synthesis RTL may have to be changed too to match the gate level and resimulated to make sure RTL simulations still pass without any issues.

False paths are paths that we don’t care about timing and they can be used to waive timing violations of such paths

Yes, good realistic timing constraints have to be created + any unconstrained paths that need to be constrained for timing have to be considered otherwise Synthesis here may show pass which in reality could be failed (due to those unconstrained paths not been exercised and they could be potential critical paths that could fail timing)

Shamin says:

Is it possible to capture this problem in gate unit delay simulations ??

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