System-Level Design
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Using SLX FPGA For Performance Optimization Of SHA-3 For HLS

Standard HLS tools help convert C/C++ faster than hand optimization on SLX FPGA.

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Author: Zubair Wadood

SLX FPGA facilitates converting your C/C++ project into an FPGA bitstream easier and with higher performance. Leveraging standard HLS (High Level Synthesis) tools from FPGA vendors, SLX FPGA tackles the challenges associated with the HLS design flow. In this paper, the results of an SLX FPGA-optimized implementation of a Secure Hash Algorithm (SHA-3; also known as Keccak) are compared to a competition-winning hand-optimized HLS implementation of the same algorithm. SLX provides a nearly 400x speed-up over the unoptimized implementation and even outperforms the hand-optimized implementation by 14%. Moreover, it is also more resource efficient, consuming nearly 3.6 times less look-up tables and 1.76 times less flip-flops.

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