Kahn Process Network: Parallel Programming Without Races And Non-Determinism

By Silexica - 18 Dec, 2019 - Comments: 0

Modern personal computing devices feature multiple cores. This is not only true for desktops, laptops, tablets and smartphones, but also for small embedded devices like the Raspberry Pi. In order to exploit the computational power of those platforms, application programmers are forced to write their code in a parallel way. Most often, they use the threading approach. This means multiple parts o... » read more

Accelerating Financial Applications With SLX FPGA

By Silexica - 25 Nov, 2019 - Comments: 0

This white paper demonstrates how engineers creating FPGA-based hardware accelerators for financial market models can take advantage of SLX FPGA. SLX FPGA can be used to accelerate optimization efforts for financial market models targeting option pricing. In this paper, two implementations of computation intensive models for pricing options are discussed, namely the Black-Scholes and Heston pri... » read more

Using SLX FPGA For Performance Optimization Of SHA-3 For HLS

By Silexica - 23 Oct, 2019 - Comments: 0

Author: Zubair Wadood SLX FPGA facilitates converting your C/C++ project into an FPGA bitstream easier and with higher performance. Leveraging standard HLS (High Level Synthesis) tools from FPGA vendors, SLX FPGA tackles the challenges associated with the HLS design flow. In this paper, the results of an SLX FPGA-optimized implementation of a Secure Hash Algorithm (SHA-3; also known as Kecca... » read more

Pushing Performance: Analysis and Optimization of Multicore Communication with SLX

By Silexica - 29 May, 2019 - Comments: 0

In theory, multicore programming should be simple: Tasks are placed on available cores and allocated a data buffer in the shared memory to communicate data between two tasks. However, the amount of communication resources in the latest multicore SoC is very limited. One cannot deal with all the data communications required by all the tasks without being able to understand communication conte... » read more

Multicore Software Design For An LTE Base Station

By Silexica - 27 Mar, 2019 - Comments: 0

This paper presents a typical base station design scenario, where decisions about HW/SW partitioning, the number of processing elements, and operational system parameters, among other things, need to be made early on by system architects. SLX determines the impact of these various design decisions and parameter selections, while exploring different target architecture configurations and checks ... » read more

How Many Cores? (Part 2)

By Ed Sperling - 21 Mar, 2016 - Comments: 1

New chip architectures and new packaging options—including fan-outs and 2.5D—are changing basic design considerations for how many cores are needed, what they are used for, and how to solve some increasingly troublesome bottlenecks. As reported in part one, just adding more cores doesn't necessarily improve performance, and adding the wrong size or kinds of cores wastes power. That has s... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.