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An open-source ISA used in designing integrated circuits at lower cost.


RISC-V is a free and open ISA (instruction set architecture) used in designing integrated circuits at lower cost based on RISC (reduced instruction set computer). RISC-V follows the open-source model with a modular design. All the base instructions are frozen, which means the hardware is stable and the software will be able to work on RISC-V chips everywhere and forever, in theory. However, RISC-V is also an extremely customizable ISA. More innovation can happen in the microarchitecture and software, when the hardware ISA is set. Designs can be optimized for power, security, and performance  that are not tied to a specific commercial processor core but run on other RISC-V CPUs.

RISC-V came out of academia, specifically the Parallel Computing Laboratory (Par Lab) at the University of California at Berkeley. According to RISC-V International, Prof. Krste Asanović and graduate students Yunsup Lee and Andrew Waterman started the RISC-V instruction set in the Par Lab in May 2010. Prof. David Patterson was director of Par Lab. The idea was to find a common architecture that cut the cost of chip development. (Here’s a blog about the 10th anniversary of RISC-V on May 18th, 2020. According to the blog, May 18th 2010 is the day the Par Lab group decided to make its own ISA.)

Arm is seen as a competitor mainly because it is still early days for RISC-V right now, and RISC-V is popular in embedded systems. Adoption of RISC-V started with smaller cores but Linux-based larger cores can be used now. In recent years, RISC-V has also branching into AI uses — for instance as accelerators — and holds promise for a broad range of markets. Companies are now specializing in adapting the microarchitecture using RISC-V ISA and offer adaptions to customers. The automotive market is becoming interested in RISC-V but full safety-critical, automotive certified RISC-V uses may be a few years off.

The ISA has become popular in China and North America, followed by Europe.

Open-source ISA, software and hardware ecosystem is extensible, modular, customizable, and flexible. The ISA, which are hard to create, is available to all and cuts cost and development time. It is hard to develop on a commercial ISA, which are bound up with IP rights that can not be shared openly. The microarchitecture, however, is not open source, which is where chip architects can design something custom for a client, such as many tiny cores or one large core. The real value that RISC-V brings is the promise of an ecosystem and the opportunity for experts within the industry to collectively work on the ISA’s future.

The RISC-V specification is designed to be extensible, and allows for many architectural extensions during implementation, but making verification frameworks equally extensible and portable can be challenging. Its long-term success will depend on levels of cooperation never seen before in the semiconductor industry. The RISC-V ISA can be customized, but that means the ISA then needs to be verified that nothing is broken. Since each RISC-V vendor has a different approach to implementing the ISA, verification is always built in. Tools, frameworks and methods are available for the test and verification process but it is still a work in progress.

Industry organizations
RISC-V International is an international non-profit organization that manages the standards for RISC-V and cultivates an open-source software and hardware ecosystem. The “RISC-V” trade name is a registered trade mark of RISC-V International. Originally called the RISC-V Foundation, a non-profit founded by members in 2015, the foundation entered a joint collaboration agreement with the Linux Foundation in 2018. RISC-V International incorporated in Switzerland in March 2020.

More info about the history can be found here.

Extensions are continually being developed and added to the standard. RISC-V International provides a list of recently ratified extensions.

RISC-V tag on Semiconductor Engineering.


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