RISC-V: More Than a Core

Interest in the open-source ISA marks a significant shift among chipmakers, but it will require continued industry support to be successful.


The open-source RISC-V instruction set architecture (ISA) is attracting a lot of attention across the semiconductor industry, but its long-term success will depend on levels of cooperation never seen before in the semiconductor industry. The big question now is how committed the industry is to RISC-V’s success.

The real value that RISC-V brings is the promise of an ecosystem and the opportunity for experts within the industry to collectively work on the ISA’s future. That ecosystem may not exist yet, but a roadmap for the future—much like the Moore’s Law roadmap that drove fabrication technology for more than a half-century—does exist.

The Moore’s Law roadmap is running out of road, though, which is why there are so many architectural innovations showing up across the industry. At the recent Hot Chips 30, dozens of new chip architectures were on display featuring multiple processors, new memory configurations and different packaging approaches. As HP Labs research scientist R. Stanley Williams recently observed, “The end of Moore’s Law could be the best thing that has happened in computing since the beginning of Moore’s Law. Confronting the end of an epoch should enable a new era of creativity.”

One of the big benefits of RISC-V is that the architecture is open source. “With RISC-V, any innovation that happens in the hardware, by collaboration, will create an economic benefit that will be massive,” says Ted Speers, head of product architecture and planning for the Programmable Solutions business unit at Microsemi. “But who gets rewarded, or how the rewards get funneled, still has to be figured out.”

Fig 1. Design costs at recent nodes. Source: Handel Jones, IBS

This is not about being cheaper. “License fees are a small part of leading-edge SoC design costs,” says Linley Gwennap, principal analyst at The Linley Group. “Architectural and IP Qualification represent less than 15% of design costs. And of that 15%, CPU costs are a small fraction. Why would anyone risk hundreds of millions of dollars to save $1 million?”

Gwennap can point to many attributes where RISC-V looks to be inferior to other competing architectures today. Still, companies throughout the ecosystem are adopting the core even without that many proof points existing.

Adopters are looking at the long-term picture. “It is a big mistake to look at RISC-V implementations and technology and do a point-to-point comparison with what you can get from some other vendor,” says Krste Asanovic, co-founder and chief architect of SiFive and chairman of the RISC-V Foundation. “That is not why people are jumping onto RISC-V. They see the way things are going to be going in the future and can see the direction.”

So why are early adopters jumping in now? “You are choosing freedom in the future,” adds Asanovic. “Early adopters do not want to be locked-in in any way and they are prepared to overlook the current status.”

That message appears to be resonating. “Custom silicon has been in the doldrums over the past 10 years because of the costs and complexity,” says Kevin McDermott, vice president of marketing for Imperas. “But new markets, such as AI and IoT, have created a huge volume potential and the smaller requirements of these devices point to where a custom device is now back on the table.”

The right target
Still, the RISC-V architecture has somewhat limited targets while the ecosystem is being developed. “The best solution is not where there are tons of legacy applications where backward compatibility and runtime consistence is necessary,” says Martin Scott, CTO for Rambus. “The closer you get to the edge—or the more you would like to control security properties or some special acceleration functionality or some niche application where you are doing something new or autonomous for the first time—that is where it gets really interesting.”

And it is not just about a single product. “People want a standard software base across their products,” adds Asanovic. “With the other vendors, their cores may be good in one domain or a few domains, but you finish up picking a different core for every application.”

This is one of the reasons that vendors such as Arm, Intel and Synopsys (ARC) and Cadence (Tensilica) have fared so well in the past. They provide much of the necessary infrastructure and ecosystem support, including deep working relationships with all of the major foundries and certifications for a large number of manufacturing processes.

“The alternative is taking out a very large architectural license from a rather closed ecosystem,” points out Scott.

Microsemi’s Speers agrees. “The starting place for a lot of companies with RISC-V is small implementation for control cores within larger SoCs. People start with small implementation and what they are building is their own ecosystem that can be customized with different aspects of their SoCs.”

That correlates with what SiFive is seeing. “We have requests for tiny cores that clock really fast and big cores that don’t run as fast,” says Asanovic. “There is demand for this flexibility, and no single vendor can provide all of that. But nobody wants to rebuild their software stack just to have a different-shaped core in some product. They want a unified software story, but with a great variety of implementations available.”

The business model
This implies a different business model. “The old model was that you choose a vendor of the core and you get their ISA,” says Asanovic. “The new model is, ‘I choose RISC-V and then I choose the vendor. I can use a different vendor for every chip, for each product. I can build my own cores. I can use an open source core or a commercial supported core from one of a number of vendors.'”

That provides a significant level of design flexibility, which contrasts sharply with increasingly restrictive design rules imposed by device scaling at the most advanced process nodes.

“It is the pliability and flexibility with a lot of transparency around the architecture in places where it is likely you will be able to do things that you otherwise would not do, or do in a way that is highly differentiated,” says Rambus’ Scott. “It is the ability to start at an atomic level and do it the right way, as opposed to the way that someone else decided for you.”

This level of flexibility has not existed in the past. “They were smart because they made the ISA open source, not the micro-architecture,” asserts Speers. “A previous project, open core 32, was a vibrant open-source hardware group in Europe. But what they made open was an implementation of a processor. With RISC-V, what is open is the instruction set, and you can use that to implement anything from the smallest IoT device to server-class processors. There will be open-source IP for RISC-V. There will also be commercial IP that may have proprietary implementations of RISC-V, but they themselves will have different business models than the IP vendors had in the past.”

This is what is really driving excitement around the RISC-V architecture. “Some of the activity around RISC-V is giving that sense of independence,” says McDermott. “I can invest now in what I believe is a great solution, and through compliance and compatibility I will have options to re-use that investment elsewhere.”

However, this calls for cooperation at levels never seen in the past. Cooperation has to exist within the industry and between industry and academia, and this is where Asanovic puts on his third hat as professor at UC Berkeley. “RISC-V came from academia, and it has always been impossible to build chips using industrial ISAs. They were too complicated, and they were locked up by IP rights. You could not share your work with others. In academia, you like to build upon what others make. We created RISC-V to enable the research we wanted to do, and then it got adopted in industry. Now what happens in industry gets fed back into academia. Now software is ported, distributions are available, the university research groups can use this ISA which they can modify with a full stack of software that is commercially supported. There is a virtuous cycle of development in universities, deployed in industry, industry finds problems, they get sent back to academia to solve and they can be re-used straight away.”

Some problems were, in fact, discovered. “Researchers at Princeton did some work and could show that while there was not a bug in the RISC-V memory consistency model, there were some missing parts to the stack that could be added to make it rock-solid,” says Speers. “Because there were researchers looking at RISC-V, and because it was all open, it developed a very robust memory consistency model. This is something that everyone will now benefit from.”

That also makes university graduates more relevant to hiring companies. “There is a closer technical alignment between the groups, and academia has been teaching topics such as novel architectures for many years,” points out McDermott. “Students can offer things that are state of the art and relevant and useful. What every graduate wants to do is to go into a job interview with some credentials to show that they are a useful hire with relevant experience. There is a merging of outlooks, and this is great for our industry.”

It also is spurring cooperation within the industry. “Historical competitors are working together more than in the past,” says Scott. “Culturally, I am encouraged that it is spurring collaboration and excitement that I haven’t seen for a long time. That does not guarantee good results. We are also seeing people come out of the woodwork in academia because it has created a connection with someone interested in consuming what they are doing. It is creating the potential to close some of the divide, particularly in the area of security.”

Hardening the hardware
Many people will require more than just an ISA, however. “A blank sheet of paper is a daunting task,” says McDermott. “One advantages of RISC-V is that if I can give you 90% of the solution, and you can modify it, then it gets the juices flowing and you don’t have to reinvent the wheel because you have an infrastructure and foundation. But you can provide something on top of it.”

Still, care has to be taken to not grow the core and add extra baggage. “There is a core that is very simple, that will always be there and will be a stable base upon which people can build. And they can rely on tools being available long into the future,” explains Asanovic. “It is modularized so you only include the modules that you need. But it is designed to be extensible in many ways, with standard extensions that the foundation will bless, and then custom extensions that a project may add.”

The number of extensions will grow over time. “RISC-V’s success is encouraging more open-source collaboration in hardware projects,” says Allen Baker, lead software developer at ANSYS. “Nvidia has open sourced their deep-learning accelerator, and integrated it into a RISC-V SoC. The Piccolo cores from Bluespec have been released to the public. Western Digital has promised to support the open-source community. Beyond standard CPUs and SoCs, vector instruction extensions are spurring development of GPUs, neural networks and other many-core architectures. The openness and extensibility of the standard enables it to grow into almost any application. Basically, any programmable component can adopt RISC-V to take advantage of the growing software toolset.”

It takes a lot of effort to prepare a core for some markets. “For RISC-V as an architecture to succeed in areas like automotive, RISC-V must be a commercial success and not just a feel-good story,” says Chris Jones, vice president of marketing for Codasip. “ISO 26262 is an expensive proposition for IP suppliers requiring tremendous financial and human capital commitments. Only successful IP providers will be able to make such investments.”

Software ecosystem
Long-term success will depend on a strong software ecosystem. “While the ecosystem is not yet as filled out as Arm, it has likely surpassed other third-party processor IPs,” says Neil Hand, director of marketing for Mentor, a Siemens Business. “This is due to the number of companies, including high-profile IP vendors, that are adopting the standard and are moving to the platform.”

The move has a good economic foundation. “The maintenance of processors and tool chains has become cost-prohibitive to most, thus an attractive candidate to outsource,” adds Jones. “However, outsourcing to traditional legacy processor suppliers is also an expensive proposition. These economic factors are contributing to the rise of RISC-V and to the success of companies that offer tools to support and maintain processor architectures.”

To discuss the support coming online would take a whole article. “A lot of the big blocks are doing fairly well,” says Speers. “Linux has been upstreamed. Two things are still required. One is an LLVM compiler, and the second one is a Java virtual machine. We are making good progress on operating systems, including RTOS support. The debug ecosystem is doing well. Sellers to the IP ecosystem include companies like UltraSoC, which has debug/trace capability, and they are developing partnerships. It is filling out fairly well.”

The EDA industry is beginning to respond, too. “I expect that the RISC-V ecosystem will extend beyond IP,” says Tom Anderson, technical marketing consultant for OneSpin Solutions. “The numerous implementations offer opportunities and users for EDA vendors. This is a brand-new ISA, so there is already considerable interest in formally verifying implementations against the ISA. I expect EDA vendors to offer verification IP (VIP) and formal apps to help their users verify their RISC-V designs.”

“The transition from academic research to commercial application requires a leap not unlike a new product crossing the chasm,” points out Dave Kelf, CMO for Breker Verification Systems. “Elements are required, such as an extensive compliance capability and commercial grade tools, and these are coming. A virtuous circle is required where commercial companies drive a robust ecosystem, which in turn convinces other companies to initiate projects.”

The increasing irrelevance of Moore’s law is impacting many aspects of the semiconductor industry. RISC-V is an indication of just how far the industry is willing to look for alternatives. As most industry insiders will attest, this clearly is not business as usual.

While it may be too early to declare RISC-V a success, it is on a solid path to get there and momentum builds. To quote Churchill—”Now this is not the end. It is not even the beginning of the end. But it is, perhaps, the end of the beginning.”

The next two years will be exciting. Jones predicts that “2019 will be the year where you will see a lot of high-profile RISC-V design wins in application areas previously dominated by legacy architectures.”

Related Stories
RISC-V Inches Toward The Center
Access to source code makes it attractive for custom applications, but gaps remain in the tool flow and in software.
RISC-V Gains Its Footing
But working with this architecture has some not-so-obvious pitfalls, and new tools licensing options may be necessary


Matt Wilson says:

Great write up, Brian. Hey, if you’re up for connecting I may have some mutually beneficial information to share regarding new semi-technology and RISC-V. Cheers, Matt

Steven Douglas Gould says:

Reduced instructions set computing
operating fast with smaller instructions
specific programs running really fast,
combine this with parallella like
hardware what could happen? where
is that 1024 core at? why is he working
at DARPA now…

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