The Rapid Rise Of RISC-V


The first RISC-V Summit, which took place last month in Santa Clara, CA, appears to be a watershed for the RISC-V ecosystem. The technology is maturing and the ecosystem is growing fast – and that was reflected in the nature of the presentations and news announcements we saw. The accent has started to move to how the technology will be used in real life. UltraSoC’s announcement of a har... » read more

Week In Review: Design, Low Power


Tools OneSpin unveiled a set of formal apps for development and assessment of RISC-V cores. The RISC-V Integrity Verification Solution formalizes the RISC-V ISA in a set of SystemVerilog Assertions to verify compliance for the ISA is met. It provides a formal bug absence core assessment environment for unbounded proofs and systematic discovery of all hidden instructions or unintended side effe... » read more

5 Top Storylines For NAND Biz


2019 is expected to be a busy, if not difficult, year in the NAND flash memory market. Vendors will continue to ramp up 3D NAND, the successor to traditional 2D or planar NAND. Then, over the last year, prices for NAND have dropped with oversupply in the market. What’s in store in 2019? Vendors are expected to rush out their next-generation products. Then, there is a debate whether the... » read more

December ’18 Startup Funding: Big Rounds As 2018 Ends


During the month of December, 16 startups had private funding rounds of $100 million and up, with half of them in the mobility area. Those 16 rounds totaled $3.2 billion as the year concluded. Before the holidays, the SoftBank Vision Fund invested $500 million in Cambridge Mobile Telematics, provider of the DriveWell platform used by insurers, vehicle fleets, wireless carriers, and others to... » read more

Week In Review: Design, Low Power


RISC-V Western Digital announced big plans for RISC-V with a new open source RISC-V core, an open standard initiative for cache coherent memory over a network, and an open source RISC-V instruction set simulator. The SweRV Core features a 2-way superscalar design with a 32-bit, 9 stage pipeline core. It has clock speeds of up to 1.8Ghz on a 28mm CMOS process technology and will be used in vari... » read more

RISC-V: More Than a Core


The open-source RISC-V instruction set architecture (ISA) is attracting a lot of attention across the semiconductor industry, but its long-term success will depend on levels of cooperation never seen before in the semiconductor industry. The big question now is how committed the industry is to RISC-V's success. The real value that RISC-V brings is the promise of an ecosystem and the opportun... » read more

RISC-V Inches Toward The Center


RISC-V is pushing further into the mainstream, showing up across a wide swath of designs and garnering support from a long and still-growing list of chipmakers, tools vendors, universities and foundries. In most cases it is being used as a complementary processor than a replacement for something else, but that could change in the future. What makes RISC-V particularly attractive to chipmaker... » read more

Hybrid Memory


Gary Bronner, senior vice president of Rambus Labs, talks about the future of DRAM scaling, why one type of memory won’t solve all needs, and what the pros and cons are of different memories. https://youtu.be/R0hhDx2Fb7Q » read more

Week in Review: IoT, Security, Auto


Deals SoftBank Corp. reached an agreement with Indonesia’s Link Net to work together on Internet of Things technology. Hidebumi Kitahara of SoftBank said in a statement, “The global mobile industry is now entering the 5G era, with IoT becoming the central focal point of innovation. This partnership with Link Net shows our strong commitment to further boost technology innovation in the glob... » read more

The Week In Review: Design


Tools Mentor, a Siemens business, filled in the last of the hardware configurations for its Veloce Strato emulation family, creating a full upgrade path. Users can initially purchase only the hardware that they need (StratoTiL) and if later they require more capacity (StratoTi) or the ability to handle larger designs (StratoT), they can incrementally add the necessary hardware to their existin... » read more

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