Week In Review: Design, Low Power

AI for PCB P&R; new inference benchmarks; building big quantum simulators; memory.


MLCommons debuted the latest results for the MLPerf Inference v3.0 and Mobile v3.0 benchmark suites, which measure the performance and power-efficiency of applying a trained machine learning model to new data in data center, edge, and mobile use cases. Overall, MLCommons said the results showed both power efficiency improvements and significant gains in performance in some benchmark tests. Several startups boasted of excellent power efficiency results for their chips, including SiMa.ai and Neuchips. HPCwire examined the results and whether the benchmarks used are a good proxy of real-life models, particularly the large language models behind the recent flurry of chatbots.

A new quantum computing research project, PASQuanS2 (Programmable Atomic Large-Scale Quantum Simulation), launched with €16.6 million (~$18.0 million) in funding over the next 3.5 years from the European Union under the Horizon Europe Framework Programme. With 25 members from academia and industry, PASQuanS2 aims to develop programmable, large-scale quantum simulators with up to 10,000 individual quantum systems and demonstrate them running stably in an end-user accessible form. The initial phase will focus on development of quantum simulators with at least 2,000 atoms. “At the end of this first phase, we plan to have a quantum simulation ecosystem involving hardware platforms and corresponding bespoke software,” said project coordinator Immanuel Bloch, director at the Max Planck Institute of Quantum Optics and chair at LMU Munich. “Moreover, this ecosystem will comprise an integrated hardware supply chain helping to advance modular systems, which we will further implement as building blocks on experiments during PASQuanS2.2, and a pipeline transferring these building blocks to industrial partners for industry-driven production of quantum simulators and open online platforms.”

Lancaster University is creating a spinout company to commercialize UltraRAM, a memory technology that uses quantum resonant tunneling in compound semiconductors. According to the developers, the new memory combines the non-volatility of flash with the speed, energy-efficiency, and endurance of DRAM.

SiPearl raised €90.0 million (~$98.5 million) in Series A funding to build an Arm-based energy-efficient microprocessor for high-performance computing. Designed to work with any third-party accelerator, SiPearl’s chips will be used in Europe’s efforts to deploy exascale supercomputers.

Find more of the latest funding news in the March Startup Funding report, which features startups building sensors with integrated AI, photonic packaging processes, and quantum computers, plus over 100 more companies in semiconductor, automotive, and related fields.

Products & tools

Cadence introduced a new tool for AI automation of PCB placement, metal pouring, and critical net routing for small-to-medium-sized designs, while ensuring the design is electrically correct and manufacturable. The company claims that Allegro X AI’s generative placement automation enables feasibility analysis in the early phases of design and reduce PCB design turnaround time.

Several companies are announcing AI-powered tools, but can the EDA industry adapt fast enough to meet all of the demands being placed on it? The space may be ripe for disruption due to rapid changes in chip architectures, end markets, and a long list of new technologies.

Kioxia and Western Digital announced 218-layer 3D flash that uses 1Tb triple-level-cell (TLC) and quad-level-cell (QLC) with four planes. It uses improved lateral scaling and CBA (CMOS directly Bonded to Array) technology, in which each CMOS wafer and cell array wafer are manufactured separately in its optimized condition and then bonded together to boost bit density and NAND I/O speed.

SureCore introduced a new range of ultra-low voltage SRAM solutions that can operate down to 0.45V. The company that because logic and memory can interface at the same voltages, they can be adjusted in tandem to increase and decrease performance and power consumption simultaneously as required by the application.

Circuit aging is emerging as a first-order design challenge as engineering teams look for new ways to improve reliability and ensure the functionality of chips throughout their expected lifetimes. But variation models from the foundries, different use cases that may stress various components in different ways, and different power and thermal profiles all makes it harder to accurately predict how a chip will behave over time.

Renesas Electronics announced new firmware for its ZMOD digital air quality sensors that allows them to be configured to support various green air quality standards for commercial and public buildings. Additionally, Renesas’ cellular-to-cloud development kits using 32-bit MCUs now support Microsoft’s Azure cloud services for connecting and managing wireless IoT devices.


Banias Labs deployed Synopsys’ 112G Ethernet PHY IP and EDA Design Suite in creation of its optical DSP SoC.

Rambus and SK Hynix extended a comprehensive patent license agreement, which will provide SK Hynix with broad access to the full Rambus patent portfolio through mid-2034.

Samsung Electronics and AMD signed a multi-year agreement extension to bring multiple generations of AMD Radeon graphics solutions to an expanded portfolio of Samsung Exynos SoCs for mobile.

Sondrel inked a multi-year license extension with Siemens for EDA software.

Research notes

A meminductor circuit element was identified by researchers at Texas A&M University. Similar to the memristor and the memcapacitor, a meminductor has a memory-like nature where its properties are dependent on previous values. The researchers demonstrated physical evidence of meminductance in a two-terminal passive system comprised primarily of an electromagnet interacting with a pair of permanent magnets.

A team from University of Southern California, University of Massachusetts, MIT, and TetraMem is building low-power AI chips that combine silicon with metal oxide memristors. Those chips use the positions of atoms to represent information rather than the number of electrons combined with a protocol to reduce noise, a technique the researchers say offers a compact and stable way to store more information in an analog and enable it to be processed where it is stored.

Magnon-based computation could lead to a computing paradigm shift, according to researchers from EPFL that found a way to send and store data using charge-free magnetic waves, rather than traditional electron flows. The team used the ferrimagnetic insulator yttrium iron garnet (YIG) to create nanomagnet devices, then were able to excite spin waves in the YIG at specific gigahertz frequencies using radiofrequency signals, and also reverse the magnetization of the surface nanomagnets. “We can now show that the same waves we use for data processing can be used to switch the magnetic nanostructures so that we also have nonvolatile magnetic storage within the very same system,” said Dirk Grundler, head of the Lab of Nanoscale Magnetic Materials and Magnonics at EPFL. “Now that we have shown that spin waves write data by switching the nanomagnets from states 0 to 1, we need to work on a process to switch them back again.”

Upcoming events

  • User2User 2023 — April 13
  • Design, Automation and Test in Europe Conference (DATE 2023) — April 17 –19
  • 2023 CMC Conference: Critical Materials Council — April 18 –20
  • CadenceLIVE Silicon Valley 2023 — April 19 –20
  • TSMC 2023 Technology Symposium — April 26
  • The Impact of New Regulations on the Semiconductor Design Ecosystem (hosted by ESD Alliance) — April 26
  • More events and webinars

Further reading

Check out the latest Low Power-High Performance and Systems & Design newsletters for these highlights and more:

  • Uneven Circuit Aging Becoming A Bigger Problem
  • What Makes RISC-V Verification Unique?
  • MIPI’s Focus Widens
  • Cooling The Data Center
  • Self-Heating Issues Spread
  • Do Necessary Tools Exist For RISC-V Verification?
  • True 3D Is Much Tougher Than 2.5D
  • The Race Toward Mixed-Foundry Chiplets
  • Managing EDA’s Rapid Growth Expectations

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