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Week In Review: Design, Low Power


Tools & IP Imperas Software introduced the RISC-V Verification Interface (RVVI). The open standard and methodology can be adapted to any configuration permitted within the RISC-V specifications. RVVI defines interfaces between RTL, reference model, and testbench for RISC-V design verification, with the aim of making RISC-V processor DV reusable. It supports multi-hart, superscalar, and out... » read more

Week In Review: Auto, Security, Pervasive Computing


From pandemic to war — some of the news this week highlights reactions to Russia’s invasion of Ukraine. Pervasive computing, IoT, 5G and beyond SpaceX sent Starlink satellite dishes to Ukraine to enable Ukrainian access to the Internet. The caveat is the uplink signals from satellite equipment can be used to triangulate the position of the dish, which can then be hit by missile. The dis... » read more

Startup Funding: December 2021


Chinese startups dominated last month's fundraising, with companies from the country comprising about two-thirds of those covered in this report. In addition to the number of companies, startups from China also drew significant amounts of funding, with a display driver company and an EV battery maker each garnering around $1B and six more companies seeing rounds over $100M. Two particularly ... » read more

Week In Review: Design, Low Power


Tools & IP Codasip unveiled three commercially licensed add-ons to the Western Digital SweRV Core EH1, aiming to allow it to be designed into a wider range of applications. The SweRV Core EH1 is a 32-bit, dual-issue, RISC-V ISA core with a 9-stage pipeline, open-sourced through CHIPS Alliance. The add-ons offer a floating-point unit (FPU) that supports the RISC-V single precision [F] and d... » read more

Week In Review: Design, Low Power


Tools & IP Codasip unveiled its Codasip SweRV Core EH1 Support Package, which provides support for Western Digital's open source RISC-V-based core. The support package provides a comprehensive set of tools and components needed to design, implement, test, and write software for a SweRV Core-based SoC with support for leading EDA open and commercial flows. A free basic version is available ... » read more