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Week In Review: Design, Low Power

RISC-V verification reuse; wafer-on-wafer AI processor; 64-bit RISC-V MPU.

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Tools & IP
Imperas Software introduced the RISC-V Verification Interface (RVVI). The open standard and methodology can be adapted to any configuration permitted within the RISC-V specifications. RVVI defines interfaces between RTL, reference model, and testbench for RISC-V design verification, with the aim of making RISC-V processor DV reusable. It supports multi-hart, superscalar, and out-of-order CPU pipelines, is compliant with UVM, and is compatible with major EDA vendor tools. “We are at the epicenter of the biggest migration of verification responsibility in the history of processor IP and EDA tools,” said Simon Davidmann, CEO at Imperas Software. “Now every SoC design team can embrace the processor design flexibility of RISC-V for optimized domain specific solutions – but this marks the end of the ‘one-size-fits-all’ era of processor IP. Expanding the scope of the established SoC verification flows to accommodate the additional complexity of RISC-V processor DV is defining the new verification ecosystem, which is unique for the adopters of the RISC-V ISA.”

SiPearl selected Ansys’ RedHawk-SC multiphysics simulation platform to validate semiconductor power integrity, minimize power consumption, and accelerate development time of its Rhea family of high-performance compute microprocessors. The HPC microprocessors will be used in the European Processor Initiative exascale supercomputing project.

Mirabilis Design uncorked the VisualSim Micro-Architecture Modeler, a solution to enable designers and verification engineers to verify the micro-architecture of the entire SoC at cycle-per-cycle. The semiconductor devices can be verified for timing, throughput, cycle per instructions, power consumption and functional correctness. Hardware engineers can verify the cause of a latency for a specific instruction across the entire SoC, or get the average latency for the Dhrystone, application-specific benchmark, or specmark. Verification using the Micro-Architecture Modeler covers the processor core, cache, interconnect, memory controller, and accelerators. Library components are used to assemble cycle-accurate and architecture-accurate models, run Monte-Carlo simulation, and receive insights into system operations. The library covers all aspects of the micro-architecture with a set of ten parameterized IP components, pre-built ARM and RISC-V cores, and reconfigurable components to create proprietary versions.

Imperas Software announced the beta release of the ImperasDV architectural validation test suites for RISC-V Physical Memory Protection (PMP). As part of the RISC-V Privileged Specification, PMP is a way to ensure memory isolation between key security applications and other activities. “In any verification plan, the opportunity to use more tests is always a useful option, but as is often the case some tests are more useful than others,” said Simon Davidmann, CEO at Imperas Software. “Test suites have many useful qualities, perhaps the top two are coverage and specification completeness. The RISC-V PMP test requirements are significant given the complexity of the specification and security implications for any implementation errors. The Imperas mutating fault simulation technology ensures the test coverage, and the Imperas reference model covers the full envelope of the PMP specification, so when combined these produce a useful architectural validation test suite for any RISC-V processor targeted at security applications.”

Breker Verification Systems debuted a framework designed to simplify specification model composition for test content synthesis with a UVM/SystemVerilog syntactic and semantic approach familiar to UVM engineers. SystemUVM layers UVM class libraries on Accellera’s Portable Stimulus Standard and uses AI planning algorithms for deep sequential bug hunting in existing UVM environments.

Chips
ASE, AMD, Arm, Google Cloud, Intel, Meta, Microsoft, Qualcomm, Samsung, and TSMC are forming an industry consortium to establish a die-to-die interconnect standard and for an open chiplet ecosystem. The consortium’s first effort, the Universal Chiplet Interconnect Express (UCIe) open specification, establishes a ubiquitous interconnect at the package level. The UCIe 1.0 specification covers the die-to-die I/O physical layer, die-to-die protocols, and software stack which leverage PCIe and Compute Express Link (CXL) standards.

Renesas introduced its new RZ/Five general-purpose MPUs built around the Andes AX45MP 64-bit RISC-V CPU core. The MPU targets IoT endpoint devices and has a maximum operating frequency of 1 GHz. Peripheral functions include support for multiple interfaces, such as two Gigabit Ethernet channels, two USB 2.0 channels, and two CAN channels, as well as dual A/D converter modules. Support is also provided for connecting external DDR memory with error checking and correction (ECC) and security functions.

MediaTek launched three new SoCs for 5G smartphones. Built on a TSMC 5nm process, the Dimensity 8100 integrates four premium Arm Cortex-A78 cores with speeds reaching 2.85GHz, while the Dimensity 8000 has four Cortex-A78 cores operating at up to 2.75GHz. Both chips use an Arm Mali-G610 MC6 GPU with MediaTek’s HyperEngine 5.0 gaming technologies, quad-channel LPDDR5 memory and UFS 3.1 storage, and MediaTek’s fifth generation AI processing unit. The third, Dimensity 1300, integrates an octa-core CPU with an ultra-core Arm Cortex-A78 clocked up to 3GHz, three Arm Cortex-A78 super cores, and four Arm Cortex-A55 efficiency cores, along with an Arm Mali-G77 GPU and MediaTek APU 3.0.

STMicroelectronics uncorked its third generation of MEMS sensors. The lineup includes barometric pressure sensors that operate from 1.7µA and have absolute pressure accuracy of 0.5hPa, 3-axis accelerometer with ultra-low power and active antialiasing, 6-axis inertial module with adaptive self configuration, and pressure sensors. Extra features on selected variants include ST’s machine learning core and electrostatic sensing.

Kandou began volume production of the second variant in its USB4 retimer family. A package-only variant of KB8001, the KB8002 retimer solution for Thunderbolt 3, USB4, USB3.2, and DisplayPort 1.4a protocols aims to simplify PCB routing and provide improved PCB channel performance for more flexible retimer placement.

Nvidia reportedly suffered a cyberattack. The company acknowledged the incident, but added no other details. A hacking group claimed credit for the attack, saying it stole data from the company in retaliation for cryptocurrency rate limiters used in consumer graphics cards. This has not been confirmed by Nvidia.

AI hardware
Graphcore unveiled its Bow intelligence processing unit (IPU), a 3D wafer-on-wafer processor, which it says will provide up to 40% better performance and 16% better power efficiency for real-world AI tasks compared to its predecessor. In the WoW processor, two wafers are bonded together to generate a new 3D die: one wafer for AI processing, which is architecturally compatible with the GC200 IPU processor with 1,472 independent IPU-Core tiles, capable of running more than 8,800 threads, with 900MB of in-processor memory, and a second wafer with power delivery die. The company said that adding deep trench capacitors in the power delivery die right next to the processing cores and memory made power delivery more efficient. The Bow IPU is used in the company’s next generation of AI computer systems, available in configurations of up to 350 PetaFLOPS of AI compute. Graphcore also said that it is working on its next generation of IPU technology, with the goal of building a machine capable of 10 exaflops of AI floating point computing and up to 4 petabytes of memory with bandwidth of over 10 petabytes/second.

Memory & storage
Industrial Technology Research Institute (ITRI) and University of California Los Angeles (UCLA) are collaborating on research, development, and industrialization of Voltage Control Magnetic RAM (VC-MRAM). According to ITRI, VC-MRAM has 50% higher writing speed and 75% less energy consumption compared to SOT-MRAM, making it suitable for AIoT and automotive applications.

Silex Insight launched 100Gbps DDR encrypter IP for on-the-fly encryption and authentication to external memory. Supporting both ASICs and FPGAs, the core is portable and configurable for various size, throughput, and latency trade-offs. “The unique architecture enables a high level of flexibility and allows it to be used by microcontroller and multi-core architectures. The features required by a specific application can be taken into account in order to select the most optimal configuration for any FPGA or ASIC technology,” said Sébastien Rabou, CTO at Silex Insight.

Microchip Technology debuted a new PCIe Gen 5 NVMe SSD controller. The Flashtec NVMe 4016 controller for high-reliability, high-performance SSDs delivering greater than 14 GB per second throughput and over 3 million IOPS. The NVMe 2.0-compliant controller offers 16 high-speed programmable NAND Flash channels capable of up to 2400 MT/s, Credit Management technology for quality of service, support for Zoned Name Spaces (ZNSs) and cloud Open Compute Platform (OCP), security features including PCIe link encryption, and a flexible architecture for evolving NVMe specifications.

Micron Technology started sampling a 176-layer NAND SSD for the data center. The Micron 7450 SSD with NVMe has latency at or below 2 ms in common, mixed, random workloads and is available in multiple form factors and capacity options.

Power devices
Altair acquired Powersim, a provider of simulation and design tools for power electronics, including power supplies, motor drives, control systems, and microgrids. “Powersim has established a powerful solution that has proven to reduce development costs and time-to-market for thousands of customers around the globe including major companies in the automotive, aerospace, consumer electronics, and industrial applications sectors,” said James R. Scapa, founder and chief executive officer, Altair. “The addition of Powersim’s technologies and experienced technical team, who has deep domain knowledge in power electronics, rounds out Altair’s offerings for electric motor design and many other applications.”  Powersim’s software will be integrated into Altair’s Electronic System Design suite. Founded in 1994, Powersim is based in Rockville, Maryland. Terms of the deal were not disclosed.

Infineon released new discrete power MOSFETs, the PQFN 2 x 2 mm 2 OptiMOS 5 25 V and 30 V product family. Optimized for synchronous rectification in SMPS (Switched Mode Power Supply) for servers, telecom bricks, portable chargers, and wireless charging, the power MOSFET is also designed for electronic speed controls (ESC) for small brushless motors in drones that require smaller form factors and lighter components.

Alpha and Omega Semiconductor released a new product in the family of coil drivers for wireless charging transmitter circuits of up to 50W. Packaged in a thermally enhanced QFN 4 x 4 package, AOZ32034AQV is designed for wireless charging applications in charging stations, cordless power tools, vacuum cleaners, drones, and other consumer electronic equipment.

Teledyne e2v HiRel uncorked its new TD99102 UltraCMOS High-speed FET and GaN transistor driver with switching speed of 20 MHz. It is designed to control the gates of external power devices such as high reliability GaN HEMTs in DC-DC, AC-DC converters, orbital Point-of-Load modules, and space motor drives. The company also released new space screened versions of its 650 V, 60 A high reliability GaN HEMTs.

Wireless & networking
CEVA introduced RivieraWaves Wi-Fi 6 Access Point (AP) IP. The IP provides a complete digital PHY and MAC layers solution for IEEE 802.11ax in a 2×2 configuration, supporting up to 160MHz bandwidth and a throughput of up to 2401Mbps (at MCS11-2SS-160MHz). It supports a toolbox of AES-CCM /GCMP, RC4, and WPI crypto accelerators as well as features to enhance medium usage like the preamble puncturing, target wake time (TWT), fragmentation, and 1024 QAM. It is provided with an integration-ready platform containing an optional open-source RISC-V processor and is operating system agnostic.

Samsung Electronics, Dell, Hewlett Packard Enterprise, Intel, Red Hat, and Wind River are teaming up on a 5G virtualized RAN (vRAN) ecosystem with the aim of driving multiparty collaboration and innovation in software-based networks. The ecosystem intends to help in the preparation for commercial deployments by aligning solution roadmaps from multiple vendors, fostering a fully interoperable approach to vRAN, and leading the design process of an end-to-end vRAN solution.

NTT DOCOMO used Keysight’s open radio access network architect (KORA) to establish a 5G Open RAN Ecosystem testbed with a virtual RAN (vRAN) verification environment. The 5G Open RAN Ecosystem test lab offers companies the ability to address a range of test, verification, interoperability, and optimization needs. “Establishing a thriving 5G Open RAN Ecosystem is critical to the success of the O-RAN standard, which makes it possible to deploy a multi-vendor infrastructure in support of operator roll-out plans across different use case requirements,” said Kalyan Sundhar, vice president and general manager for Keysight’s 5G edge to core industry group.

Qualcomm made a slew of announcements, among them its Snapdragon X70 with a 5G Modem-RF System that uses AI to optimize sub-6 GHz and mmWave 5G links for improved speeds, coverage, latency, mobility, link robustness, and power efficiency. It includes spectrum aggregation capabilities and standalone mmWave support. The company also uncorked its Wi-Fi 7 product with Dual Bluetooth, which benchmarked at peak speeds of 5.8 Gbps and sub-2 millisecond latency. It includes High Band Simultaneous (HBS) Multi-Link technology for multiple 5GHz and 6GHz connections while reserving high-traffic 2.4GHz spectrum for Bluetooth and lower-bandwidth Wi-Fi. Qualcomm, Foxconn Industrial Internet, and Quectel also introduced Snapdragon X65 and X62 5G M.2 Modules for 5G-enabled laptop and desktop computers. Finally, Qualcomm is working with numerous other companies on 5G Open RAN and virtualized RAN deployments.

Marvell introduced its Alaska A PAM4 DSP family for Active Electrical Cables (AECs). Fabricated in 6nm process, the 400G/800G AEC DSPs can compensate for >40db of loss for longer reach and thinner cables. The AEC platform includes a complete cable reference design for 400G and 800G AECs and software stack with CMIS5.0 support. Marvell also announced a 800Gbps or 8 x 100Gbps multimode platform solution that includes PAM4 DSP with a multimode transimpedance amplifier (TIA) and Driver for short-reach optical modules and Active Optical Cable (AOC) applications.

Quantum computing
Hybrid quantum-classical computing developer Rigetti Computing is now a public company, trading on Nasdaq as RGTI, after the completion of its merger with special-purpose acquisition company Supernova Partners Acquisition Company II. As a result of the merger, Rigetti received gross proceeds of approximately $261.75 million, which will be used to accelerate its development of multiple generations of quantum processors, expand its operations, and for general corporate purposes.

Automotive
Infineon launched new EDT2 IGBTs in a TO247PLUS package. The devices are optimized for automotive discrete traction inverters with a breakdown voltage of 750 V, support for battery voltages up to 470 V DC, and lower switching and conduction losses. The rated currents of the discrete EDT2 IGBTs are 120 A and 200 A at 100°C, each with a very low forward voltage, reducing conduction losses by up to 13% compared to the previous generation.

Honda adopted Renesas’ R-Car automotive SoC and RH850 automotive MCU for its Honda SENSING Elite system featured in the Legend sedan and will also use them in its SENSING 360 omnidirectional safety and driver assistance system.

Fixstars Corporation and Renesas will establish an Automotive SW Platform Lab tasked with the development of software and operating environments for Renesas automotive devices. The new Lab will support early development and ongoing operation of ADAS and autonomous driving systems, including developing technologies aimed at software development for deep learning and building operating environments that have the ability to continuously update learned network models to maintain and enhance recognition accuracy and performance. “After developing a deep learning application, it is not possible to maintain high recognition accuracy and performance without constantly updating it with the latest learning data,” said Satoshi Miki, CEO of Fixstars. “Fixstars plans to focus on these machine learning operations (MLOps) for the automotive field, as we work together with Renesas to develop a deep learning development platform optimized for Renesas devices.” Additionally, Renesas and Tata Elxsi jointly established a design center in Bangalore that will develop targeted solutions for electric vehicles, developing reference designs and solution accelerators for critical EV subsystems such as Battery Management Systems and Motor Control Units.



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