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Week In Review: Design, Low Power


Tools, IP, design Infineon Technologies acquired NoBug, a provider of design verification services. The acquisition will help Infineon expand its IoT R&D business in eastern Europe. “This considerable increase in superior verification know-how lets Infineon offer its customers more of its leading products at a reduced time-to-market,” said Guenter Krasser, Vice President and Managing D... » read more

Week In Review: Design, Low Power


IP, design Arm unveiled a number of new CPUs and GPUs. Based on the Armv9 architecture, the Cortex-X3 aims to improve single-threaded performance and targets a range of benchmarks and applications. The Cortex-A715 focuses on efficient performance, delivering a 20% energy efficiency gain and 5% performance uplift compared to Cortex-A710. In addition, the Cortex-A510 and DSU-110 were updated to ... » read more

The Changing Mask Landscape


Semiconductor photomasks have undergone some major technology changes in the past few years after relatively minor changes for many years. New technologies such as multi-beam mask writers and extreme ultraviolet (EUV) lithography are major breakthroughs as they ramp into high-volume manufacturing. A new trend related to these technologies is the use of curvilinear features on photomasks. Aki... » read more

Blog Review: March 9


Arm's Ajay Joshi investigates how to select the right benchmark for CPUs used in the Home device market, such as digital television and set-top box/over-the-top devices. Ansys' Jon Kordell checks out how reliability physics simulations and physical component characterization can support component swapping in high-reliability applications when the original part is unavailable due to supply ch... » read more

Week In Review: Design, Low Power


Tools & IP Imperas Software introduced the RISC-V Verification Interface (RVVI). The open standard and methodology can be adapted to any configuration permitted within the RISC-V specifications. RVVI defines interfaces between RTL, reference model, and testbench for RISC-V design verification, with the aim of making RISC-V processor DV reusable. It supports multi-hart, superscalar, and out... » read more

A review of interconnect materials used in emerging memory device packaging: first- and second-level interconnect materials


Abstract "The main motivation of this review is to study the evolution of first and second level of interconnect materials used in memory device semiconductor packaging. Evolutions of bonding wires from gold (Au) to silver (Ag) or copper (Cu) have been reported and studied in previous literatures for low-cost solution, but Au wire still gives highest rating in terms of the performance of tempe... » read more

Memory Technology: Innovations needed for continued technology scaling and enabling advanced computing systems


Abstract: "An increasing demand for data generation, storage, and intelligence generation from data is driving advances in memory technology and advanced computing applications. Memory performance is starting to define modern day computing in both mobile and server environments. There is an absolute need to continue the tremendous pace of memory technology improvements to deliver performanc... » read more

What About Mask Rule Checking For Curvilinear Photomasks?


The entire photomask design chain needs to be considered in the adoption of curvilinear photomasks. A broad look at the ecosystem impact was addressed in a previous video but a more in-depth look at the design chain of photomasks raises the next question – will MRC be harder and take more time? Aki Fujimura of D2S opens the nine-minute panel video with industry luminaries by providing a conce... » read more

Micron D1α, The Most Advanced Node Yet On DRAM


Finally, we got to see D1α DRAM generation! It’s 14nm! After a quick viewing of the Micron D1α die (die markings: Z41C) and its cell design, we have determined its actual technology node (design rule), in contrast to the claims of market literature. It is the most advanced technology node ever on DRAM, and it is the first sub-15nm cell integrated DRAM product. The Micron Z41C die removed... » read more

Developing A New Curvilinear Data Format


The data size generated by curvilinear masks could impact turnaround time (TAT) for photomask production and hence the adoption of curvilinear masks. In a previous blog on curvilinear masks, our panel of luminaries discuss some possible solutions in a video discussion. In this seventh video, the panel looks at some ideas to define a new curvilinear data format to reduce file sizes. Aki Fujimura... » read more

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