tag: Mirabilis Design

Anatomy Of A System Simulation
By Brian Bailey - 26 Oct, 2023 - Comments: 0

The semiconductor industry has greatly simplified analysis by consolidating around a small number of models and abstractions, but that capability is breaking down both at the implementation level and at the system level. Today, the biggest pressure is coming from the systems industry, where the electronic content is a small fraction of what must be integrated together. Systems companies tend... » read more

Industry Pressure Grows For Simulating Systems Of Systems
By Brian Bailey - 28 Sep, 2023 - Comments: 0

Most complex systems are designed in a top-down manner, but as the amount of electronic content in those systems increases, so does the pressure on the chip industry to provide high-level models and simulation capabilities. Those models either do not exist today, or they exist in isolation. No matter how capable a model or simulator, there never will be one that can do it all. In some cases,... » read more

Week In Review: Design, Low Power
By Jesse Allen - 24 Jun, 2022 - Comments: 0

RISC-V RISC-V International announced four new specification and extension approvals. Efficient Trace for RISC-V defines an approach to processor tracing that uses a branch trace. RISC-V Supervisor Binary Interface architects a firmware layer between the hardware platform and the operating system kernel using an application binary interface in supervisor mode to enable common platform services... » read more

AI-Powered Verification
By Brian Bailey - 01 Jun, 2022 - Comments: 1

With functional verification consuming more time and effort than design, the chip industry is looking at every possible way to make the verification process more effective and more efficient. Artificial intelligence (AI) and machine learning (ML) are being tested to see how big an impact they can have. While there is progress, it still appears to be just touching the periphery of the problem... » read more

Week In Review: Design, Low Power
By Jesse Allen - 04 Mar, 2022 - Comments: 0

Tools & IP Imperas Software introduced the RISC-V Verification Interface (RVVI). The open standard and methodology can be adapted to any configuration permitted within the RISC-V specifications. RVVI defines interfaces between RTL, reference model, and testbench for RISC-V design verification, with the aim of making RISC-V processor DV reusable. It supports multi-hart, superscalar, and out... » read more

Week In Review: Design, Low Power
By Jesse Allen - 29 Jan, 2021 - Comments: 0

The CXL Consortium published the Compute Express Link 2.0 specification. CXL is an interconnect that maintains memory coherency between the CPU memory space and memory on attached devices. CXL 2.0 adds support for switching for fan-out to connect to more devices, memory pooling for increased memory utilization efficiency and providing memory capacity on demand, and support for persistent memory... » read more

Week In Review: Design, Low Power
By Jesse Allen - 05 Oct, 2018 - Comments: 0

Mirabilis Design debuted an AI-driven tool for performance analysis and architecture exploration of SoCs and embedded systems. VisualSim AI Processor Generator creates pipeline-accurate models that have port integration with standard buses and memories, which is used to compare different processor families, optimize the specification and identify system bottlenecks. The generated model supports... » read more

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