Week In Review: Design, Low Power

Processor models; TSMC on cloud, certifications; EDA revenue up.


Mirabilis Design debuted an AI-driven tool for performance analysis and architecture exploration of SoCs and embedded systems. VisualSim AI Processor Generator creates pipeline-accurate models that have port integration with standard buses and memories, which is used to compare different processor families, optimize the specification and identify system bottlenecks. The generated model supports variable processor pipelines, SIMD/MIMD, multi-thread, multi-level cache hierarchy, coherency, heterogeneous execution units, buffers and bus interfaces. It currently supports the entire ARM and PowerPC processor families, with additional support planned for DSP and x86 architectures.

EDA and IP revenues have kept rising, according the ESD Alliance’s Market Statistics Service. In total, revenue grew to $2.39 billion in Q2 of 2018, an 8.2% increase over the $2.21 billion reported in the same period in 2017. PCB and multi-chip module revenue was $231.5%, an 18.5% increase compared with Q2 of 2017. CAE revenue was $819.9 million, up 21% compared with the same period in 2017. IC physical design and verification increased 7.5% to $466.9 million. Services revenue, meanwhile, dropped 5.4% to $103 million, a reflection of strong hiring among companies. Hiring in EDA and IP continues as well, with the number of employees increasing 9% to 41,706, up from 38,265 in Q2 2017.

TSMC Updates
TSMC launched a cloud-based design ecosystem, Open Innovation Platform Virtual Design Environment (OIP VDE). The TSMC OIP VDE’s first implementations of digital RTL-to-GDSII and custom schematic capture-to-GDSII flows are via partnerships with Amazon Web Services (AWS), Cadence, Microsoft Azure, and Synopsys. Both digital and custom design flows have been validated in the cloud, along with OIP design collateral including process technology files, PDKs, foundation IP, and reference flows. Cadence and Synopsys will provide access through their cloud solutions.

ANSYS’ RedHawk and Totem tools have been certified for TSMC’s N7+ process, including extraction, power integrity and reliability, signal electromigration, and thermal reliability analysis. The reference flow has been validated for the latest Integrated Fan-Out with Memory on Substrate (InFO_MS) advanced packaging technology. The InFO_MS reference flow includes die and package co-simulation and co-analysis for extraction, power and signal integrity analysis, power and signal electromigration analysis and thermal analysis. ANSYS also worked with TSMC on automotive reliability with a guide to proven workflows for IP, chip and package development on TSMC 7nm FinFET.

Cadence’s digital, signoff and custom/analog tools have been certified for the TSMC 5nm and 7nm+ processes. Enhancements include via pillar-aware synthesis and feed forward guidance as well as a pin-access control routing method for cell electromigration (EM) handling and statistical EM budgeting support. For analog, new features include end-to-end constraint support, dummy insertion and advanced MIMCAP support specifically for the 5nm process. Additionally, Cadence’s digital tools and advanced IC packaging solutions support the TSMC InFO_MS packaging technology.

Mentor’s Calibre nmPlatform and Analog FastSPICE Platforms were certified for TSMC’s 7nm FinFET Plus and the latest version of 5nm FinFET processes. Updates include unique fill routines and new PERC constraint checks. Additionally, Mentor is expanding features in its Xpedition products in support of TSMC’s InFO_MS packaging offering, including automation for source net list generation for running Calibre 3DSTACK for connectivity checking.

Synopsys’ Digital and Custom Design Platforms have been certified by TSMC for its 5nm EUV-based process. Updates to the suites include enhancements to via-pillar optimization, multibit banking, and pin-access optimization, as well as improved POCV analysis. The Design Platform also now supports TSMC’s WoW direct stacking and CoWoS technologies, including multi-die and interposer layout implementation as well as parasitic extraction and timing analysis coupled with physical verification. A portfolio of DesignWare Interface IP, Logic Libraries and Embedded Memories is available for the TSMC N7+ FinFET process. The IPs have seen multiple customer tapeouts on the process. Additionally, automotive-grade Controller and PHY IPs, including LPDDR4X, MIPI CSI-2 and D-PHY, PCI Express 4.0, and security IP, have been released for TSMC’s 7nm FinFET process.

Arm teamed up with Xilinx to offer Cortex-M processors for FPGA integration through the Arm DesignStart program. In particular, it gives access to Cortex-M1 (an FPGA-optimized version of the Cortex-M0 processor) and Cortex-M3 soft processor IP for integration with Xilinx FPGAs that support Vivado. The program provides a no license fee, no royalties access model.

Autotalks purchased Arteris IP’s FlexNoC Interconnect and the companion FlexNoC Resilience Package for its automotive V2X communications chipsets. “Arteris IP technology allowed us to ease our readiness for ISO 26262 compliance process,” noted Autotalks CEO Hagai Zyss.

Boeing inked a deal with Siemens to use Mentor’s technology as the basis of a company-wide platform for semiconductor design and verification, printed wire board design and manufacture, electrical system design and manufacture (including wire harness) and thermal and fluid analysis of mechanical designs.

Arm TechCon: Oct. 16-18 in San Jose, CA. The Arm-centric conference and expo will feature keynotes by senior Arm executives as well as best-practices for implementing Arm IP in a range of designs, including IoT and automotive. The company has also teased an expanded roadmap for future products to be released at the show.

ICCAD: Nov. 5-8 in San Diego, CA. The technical conference focused on emerging technology challenges in EDA features keynotes on IoT and Cloud systems, DARPA’s Electronics Resurgence Initiative, and the impact of technology trends on EDA tools and flows. Special sessions, tutorials, and workshops are also part of the program.

RISC-V Summit: Dec. 3-6 in Santa Clara, CA. The first annual conference and exhibition dedicated to the RSIC-V ISA ecosystem. Training sessions, workshops, and presentations will be available, followed by a day for Foundation members.

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