Week In Review: Design, Low Power

CXL 2.0 published; power and signal signoff for multi-die; encrypting data in HPC SoCs; RISC-V validation test suites.


The CXL Consortium published the Compute Express Link 2.0 specification. CXL is an interconnect that maintains memory coherency between the CPU memory space and memory on attached devices. CXL 2.0 adds support for switching for fan-out to connect to more devices, memory pooling for increased memory utilization efficiency and providing memory capacity on demand, and support for persistent memory. It is backwards compatible with CXL 1.1 and 1.0.

Tools & IP
Synopsys debuted DesignWare Integrity and Data Encryption (IDE) Security Modules to help protect against data tampering and physical attacks in high-performance computing (HPC) SoCs using the PCIe 5.0 architecture or Compute Express Link (CXL) 2.0 interface. The IDE Security Modules use encryption, decryption, and authentication based on AES-GCM algorithms to protect sensitive data while meeting PCIe 5.0 and CXL 2.0 IP performance and latency requirements.

Ansys released the latest version of its engineering simulation tools, Ansys 2021 R1. New in the release are enhancements for large electromagnetic system simulations that can include encrypted proprietary 3D components from vendors. It also supports power integrity, signal integrity, reliability and thermal signoff for all advanced process nodes down to 5nm and for advanced 3D multi-die system integrations, including a flow for finding and analyzing the activity vectors that give rise to the worst-case timing impact of dynamic IR drop as well as diagnostics for debugging of dynamic voltage drop issues in large chip designs. For automotive, it provides a comprehensive sensor solution for AVs, including real-time, physics-based radar sensor capability, new scanning and rotating lidar models, and closed-loop simulation validation. For electric vehicles, there’s a new battery designer tool, battery models, and EV powertrain library.

Imperas Software added to its lineup of RISC-V Verification IP solutions with Floating-Point architectural validation test suites covering the RISC-V Specifications for 32bit Single-Precision (32F), 64bit Single-Precision (64F), and 64bit Double-Precision (64D). To support the SystemVerilog encapsulation of the reference model, the VIP package includes example SystemVerilog supporting components and modules for interfacing and synchronization between the Imperas RISC-V golden reference model and the RTL core under test in a step-and-compare verification flow.

Winbond and Flex Logix teamed up, pairing Winbond’s 4Gb LPDDR4X chip with Flex Logix’s InferX X1 edge inference accelerator chip in a half-height/half-length PCIe embedded processor board for edge servers and gateways. It offers reconfigurable optimized data paths to reduce the traffic between the processor and DRAM and increase throughput and reduce latency.

Synopsys demonstrated its DesignWare 112G Ethernet PHY IP in 5nm FinFET process in silicon. The IP is placement-aware to maximize bandwidth per die-edge through stacking and placement on all four edges of the die.

Avery Design Systems released CXL 2.0 VIP. The VIP provides a System Verilog/UVM verification solution including models, protocol checking, and compliance test suites for PCIe 5.0 and CXL 2.0/1.1 for CXL host, Type 1-3 devices, switches, and retimers.

Mirabilis Design uncorked VisualSim VPS, a platform that combines the VisualSim modeling and simulation platform with the Gem5 Instruction Set. VisualSim VPS supports 32-bit and 64-bit architectures, multi-core, and out-of-order processors. Instruction sets available are ARMv7, ARM v8, ARM SVE, RISC-V, x86, Power, and CUDA GPU.

T2M IP uncorked a number of new USB PHY and Controller IP. The Controller IP covers USB 2.0 up to USB 4.0. PHY IP is available from USB 2.0 to USB 3.2 Gen2 on TSMC, UMC, and SMIC processes.

The U.S. Department of Energy is planning to spend up to $12 million to get scientific software running on the next generation of supercomputers, and in particular for parallel-programming environments, reports InsideHPC. The funding will also go to new methods of testing scientific applications to ensure they function properly on new systems. “The coming generation of supercomputers, as we move through and beyond the era of exascale computing, will bring a huge boost in capabilities for scientific investigation and discovery,” said Dr. Steve Binkley, acting director of DOE’s Office of Science. “Taking advantage of these capabilities will require adaptation to radically new computing architectures and programming environments.  This research seeks to tackle these challenges in very systematic ways.”

Hewlett Packard Enterprise won a bid for a new supercomputer for the National Center for Atmospheric Research. The machine will cost $35 to $40 million and be part of a supercomputing center in Cheyenne, Wyo. It is expected to rank in the top 25 fastest machines with a HPE Cray EX architecture and a theoretical peak performance of 19.87 petaflops, which will be put to use improving predictions of wildfires, hurricanes, and solar storms.

Xilinx reported third quarter 2021 financial results with revenues of $803 million, up 11% from $723 million in the same quarter last year. On a GAAP basis, net income for Q2 2021 was $0.69 per share, up 8% from Q3 2020. Non-GAAP net income was $0.78 per share, up 15% from the same quarter last year. Victor Peng, Xilinx president and CEO, noted the revenue exceeded the high end of guidance, adding, “Our Wired and Wireless Group performed better than expected as 5G deployments ramped more meaningfully in North America. We achieved a record quarter in Automotive, Broadcast and Consumer end markets.” Xilinx CFO Brice Hil added that the Zynq platform product revenue grew 24% sequentially to make up 27% of total revenue during the quarter.

DRAM and NAND flash are expected to be the two fastest-growing product segments in 2021, according to market research firm IC Insights, with sales growing by 18% and 17% respectively. Closely following are two categories of automotive ICs (application-specific analog and special purpose logic), which are each expected to grow 16% in 2021 as vehicle purchases rebound.

If the automakers can get enough chips, that is: the shortage has prompted the German government to request help from Taiwan’s Ministry of Economic Affairs in pushing foundries to make more auto chips, according to Taiwan Times. TSMC responded by promising to prioritize production of auto chips if it is able to further increase capacity through optimization of the production process, reported Reuters. UMC also said it is trying to address the shortage, saying that its fabs are running at full utilization but that some capacity increase could come from productivity improvement, which would probably be allocated to auto chips.

Non-profit tech incubator EvoNexus is partnering with Arm to provide startups no-cost access to Arm IP through the Flexible Access for Startups program. “EvoNexus’ partnership with Arm arrives at a time when silicon startups have a significant opportunity to create new devices addressing a plethora of nascent markets being created through enhanced mobile broadband (5G) including IoT, mobile edge computing, automotive, telemedicine, and AR/VR/XR,” said Rory Moore, CEO, co-founder EvoNexus and founder Peregrine Semiconductor & Silicon Wave. “Since its inception, EvoNexus has excelled at launching semiconductor startups; 20 companies created and 6 acquired. Arm provides important guidance on industry trends and opportunities where startups can play a meaningful role.”

Find a new conference or learning opportunity at our events page, or check out an upcoming webinar.

Si2 will host a workshop on efforts to assess AI capacity and infrastructure, as well as application of AI for semiconductor test, on Jan. 29.

In February, the 2021 International Solid-State Circuits Virtual Conference will be held Feb. 13-22. The International Symposium on Field-Programmable Gate Arrays will take place Feb. 28-Mar. 2.

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